低複雜度與低功率MP3與其高頻重現部份之設計

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姓名

吳佳頴(Chia-Ying Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

低複雜度與低功率MP3與其高頻重現部份之設計
(A Low Complexity and Low Power MP3 Design with it's SBR Extension)

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摘要(中)

MPEG Layer 3 (MP3)是目前最為普遍的數位音訊壓縮格式，不管是在一些硬體的裝置或是軟體上的應用。最近，MP3已經成為個人數位音樂娛樂的代名詞。許多SOC (system-on-chip)系統都加入MP3當作它的附加功能，例如一些手機或隨身的裝置。市面上也有許多MP3 player的產品在販賣。由於考慮到市場的快速需求，目前一般的做法會採用DSP或是RISC processor的方式去實現。但是採用這種做法並不是一個最佳化的方式，因為它們並不是針對MP3所做的硬體設計，所以會有些多餘的電路，造成較大的功率消耗和面積。另外過多的記憶體使用量也是一個問題。
因為一些手攜式裝置上的應用，功率消耗和產品的成本變得格外重要。記憶體的使用就必須很小心規劃，因為記憶體的使用相當的耗成本以及功率消耗。我們採用了完全ASIC的方式去實現MP3解碼器，可以改善processor所產生的問題，使我們的設計達到低功率和低成本以適用於一般消費性的裝置中。
除了以ASIC做設計所產生的優點，透過仔細觀察MP3的解碼流程，我們可以進一步做改善。在本論文中，針對我們的MP3解碼器架構提出了一些降低功率的技術以及採用最精簡的記憶體使用量。
此外，我們還針對高頻重現部份做設計，採用硬體共用架構，來達到較小面積設計，以及較高的硬體使用率。

摘要(英)

MPEG Layer 3 (MP3) is the most popular audio compression format in the world for both hardware-based devices and software-based applications. Presently, MP3 has turned into a synonym for personalized music entertainment for millions of people. Based on the consideration of fast time-to-market, a general-purpose DSP or RISC processor is the common implementation approach for MP3 decoder. Since the hardware is not dedicated for MP3 application, some architecture parts in the processor are not utilized completely. The cost of each product is relatively high and the power dissipation is also a problem.
Since the MP3 decoder is targeted to fit into a small portable, it is necessary to minimize the power consumption and cost. Identically, it is always reasonable to reduce the memory requirements since memory is expensive and consumes power. By use of the pure-ASIC approach, we can provide a consumer-economical solution for MP3 audio decoder with the advantages of low-cost and low-power design. Instead of the benefits obtained from dedicated hardware design, it still exist some improvements by well analysis on the individual features of MP3 decoding. This thesis is targeted on the architecture implementation with some proposed techniques to achieve a low power and memory-optimized design.
Beside, we also design the SBR architecture using hardware sharing methods. So our design can achieve small area and high hardware utilization.

關鍵字(中)

★ 高頻重現
★ 低功率

關鍵字(英)

★ MP3
★ SBR
★ Hybrid Filter Bank
★ ASIC
★ Low Power

論文目次

摘要 i
ABSTRACT ii
致謝 iii
CONTENT iv
LIST OF FIGURES viii
LIST OF TABLES xi
CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND 1
1.2 MOTIVATION 2
1.3 MP3 ENCODER OVERVIEW 3
1.3.1 PSYCHOACOUSTIC MODEL 4
1.3.2 HYBRID FILTER BANK 5
1.3.3 BIT ALLOCATION 7
1.3.4 QUANTIZATION 7
1.3.5 HUFFMAN CODING 8
1.4 MP3 DECODER OVERVIEW 8
1.4.1 BITSTREAM PARSING 9
1.4.2 HUFFMAN DECODING 10
1.4.3 DE-QUANTIZATION 10
1.4.4 STEREO PROCESS 11
1.4.5 ALIASING PREDICTION 12
1.4.6 HYBRID FILTER BANK 12
1.5 THESIS ORGANIZATION 14
CHAPTER 2 OVERVIEW OF OUR PREVIOUS WORKS ON MP3 DECODER 15
2.1 HUFFMAN DECODING 15
2.1.1 SURVEY ON EXISTING ALGORITHM 16
2.1.2 PROPOSED ARCHITECTURE OF PREVIOUS WORKS 17
2.2 DE-QUANTIZATION 19
2.2.1 SURVEY ON EXISTING ALGORITHM 19
2.2.2 PROPOSED ARCHITECTURE OF PREVIOUS WORKS 19
2.3 STEREO PROCESS 20
2.4 HYBRID FILTER BANK 22
2.4.1 SURVEY ON EXISTING ALGORITHM 22
2.4.2 PROPOSED ARCHITECTURE OF PREVIOUS WORKS 23
2.4.3 DWIMDCT 24
2.4.4 SYNTHESIS FILTER BANK 25
CHAPTER 3 PROPOSED LOW POWER AND MEMORY OPTIMIZATION TECHNIQUES FOR MP3 DECODER 27
3.1 MODIFIED ARCHITECTURE OF HYBRID FILTER BANK 27
3.1.1 OPERATION OF HYBRID FILTER BANK 27
3.1.1.1 OPERATION OF DWIMDCT 28
3.1.1.2 OPERATION OF SYNTHESIS FILTER BANK 29
3.1.1.3 TIMING ANALYSIS ON PREVIOUS WORK 30
3.1.2 PIPELINE SCHEME BETWEEN DWIMDCT MODULE AND SYNTHESIS FILTER BANK 31
3.1.3 MEMORY HIERARCHY OF PRE-POST BUFFER AND DWIMDCT BUFFER 33
3.1.3.1 BASIC IDEA 34
3.1.3.2 ARCHITECTURE DESIGN 35
3.2 PIPELINE SCHEME BETWEEN PRE-PROCESSING UNIT AND POST-PROCESSING 35
3.2.1 GRANULE-LEVEL ANALYSIS ON TWO AUDIO CHANNELS 36
3.2.2 GRANULE-LEVEL ANALYSIS ON TWO AUDIO CHANNELS WITH PIPELINE SCHEME 37
3.3 MEMORY OPTIMIZATION OF DWIMDCT BUFFER 39
3.4 LOW POWER TECHNIQUE USING CLOCK-GATING AND OPERAND ISOLATION 41
3.4.1 CLOCK-GATING APPROACH 41
3.4.2 OPERAND ISOLATION APPROACH 43
CHAPTER 4 SPECTRAL BAND REPLICATION DESIGN 45
4.1 INTRODUCTION 45
4.1.1 WHY SBR IMPROVES AUDIO CODING 46
4.1.2 HOW SBR WORKS 48
4.2 SBR ENCODER OVERVIEW 49
4.3 SBR DECODER OVERVIEW 52
4.3.1 LOW POWER SBR 54
4.4 WELL ANALYSIS ON SBR 55
4.5 DESIGN OF HF GENERATOR 59
4.5.1 DESIGN OF LINEAR PREDICTION 59
4.5.2 DESIGN OF INVERSE FILTERING 60
4.5.3 CONFIGURATION DESIGN FOR HF GENERATOR 62
CHAPTER 5 IMPLEMENTATION ON HARDWARE PLATFORM 63
5.1 INTRODUCTION TO HARDWARE PLATFORM 63
5.1.1 INTRODUCTION TO CORE MODULE 63
5.1.2 INTRODUCTION TO LOGIC MODULE 65
5.1.3 INTRODUCTION TO INTEGRATOR/AP 66
5.2 DESIGN OF IMPLEMENTATION 67
CHAPTER 6 SIMULATION RESULTS AND COMPARISONS 70
6.1 SIMULATION RESULTS 70
6.2 COMPARISONS OF MP3 DECODER 71
6.3 SYNTHESIS RESULTS FOR FPGA 73
CHAPTER 7 CONCLUSION AND FUTURE WORK 74
7.1 CONCLUSION 74
7.2 FUTURE WORK 76
REFERENCES 77

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指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2008-3-20

推文