對於長解碼長度可降低其記憶體使用的低密度同位檢查碼解碼器設計

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廖欽寬(Chin-Kuang Lian) 查詢紙本館藏

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電機工程學系

論文名稱

對於長解碼長度可降低其記憶體使用的低密度同位檢查碼解碼器設計
(A Partially Parallel Low-Density Parity Check Code Decoder with Reduced Memory for Long Code-Length)

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摘要(中)

由於低密度同位檢查碼 (LDPC) 的編碼增益接近向農 (Shannon) 極限，而且在解碼程序上，LDPC擁有低複雜度的特性，所以在近年來受到廣泛的討論。也因此LDPC被許多標準認定為是相當傑出的錯誤更正碼進而被使用在很多不同的通訊應用上，例如：數位衛星電視(DVB-S2), 無線區域網路MIMO-WLAN (802.11n), 無線都會網路WMAN (802.16e)和行動寬頻無線接取技術(MBWA) (802.20)等等。在演算法上，LDPC解碼是使用訊息傳送的演算法，使用這樣的演算法在硬體實現上必須使用記憶體來儲存交換的訊息，而所需要的記憶體量跟同位元矩陣（H matrix）中所包含1的數量有關。換句話說，當同位元矩陣的長度越長或矩陣的大小越大則所需要的記憶體量就會越多。在此篇論文，我們提出了一種方法跟架構去減少記憶體的儲存量，而且這樣的一個方式在同位元矩陣相當大的應用—DVB-S2會有相當多的記憶體節省量。

摘要(英)

In recent years, low-density parity-check (LDPC) codes have attracted a lot of attention due to the near Shannon limit coding gains when iteratively decoded. Thus, the LDPC codes have been well recognized as an excellent error correction coding scheme for many digital communication systems, such as the next generation digital video broadcasting (DVB-S2), MIMO-WLAN (802.11n), WMAN (802.16e), mobile broadband wireless access (MBWA) (802.20) systems, and etc. Based on the message-passing algorithm, the LDPC decoder uses memories to store intermediate data between bit nodes and check nodes. In fact, the quantity of the stored data is related to the non-zero entries in H matrix. In other words, the memory size required by the LDPC decoder with the partially parallel architectures may significantly increase for large code length LDPC codes. In this thesis, we present an alternative approach which significantly reduces the memory size requirement and the salient feature of memory size reduction becomes significance particular for DVB-S2 applications.

關鍵字(中)

★ 低密度同位檢查碼
★ 解碼器

關鍵字(英)

★ LDPC Decoder
★ Parallel
★ Long Code-Length

論文目次

Abstract i
Content iv
List ofFigures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 LDPC Decoding Algorithms 3
2.1 Concept of LDPC 4
2.2 Message Passing Algorithm 5
2.3 LDPC Decoding Algorithms 7
2.3.1 Sum-Product Algorithm 7
2.3.2 Log-Likelihood Ratio for Sum-Product Algorithm 10
2.3.3 Min-Sum Algorithm 12
Chapter 3 Architectures of LDPC Decoder 15
3.1 Architectures of LDPC Decoder 16
3.1.1 Serial Architecture 16
3.1.2 Fully Parallel Architecture 17
3.1.3 Partially Parallel Architecture 18
3.1.4 Discussion 20
3.2 CNFU and BNFU 21
3.2.1 LLR-SPA 22
3.2.2 Modify Min-Sum 24
3.2.3 Discussion 25
3.3 Irregular LDPC Decoder 25
Chapter 4 Architecture Design and Circuit implementation 31
4.1 Decoder Design 32
4.1.1 Modify Min-Sum Algorithm 32
4.1.2 Architecture Overview 35
4.1.3 Value Generator Unit (VG) 37
4.1.4 Sum Generator Unit for column operation (SGU) 38
4.1.5 Minimum generator unit for row operation 39
4.1.6 Memory arrangement 41
4.1.7 Data Retrieval Scheme 42
4.1.8 Overall Architecture 44
4.1.9 Proposed Architecture for irregular LDPC 46
4.2 Experimental Results 48
Chapter 5 Conclusion 52
5.1 Summary and Conclusion 52
5.2 Future Work 54
Reference 55

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指導教授

魏慶隆、蔡宗漢
(Chin-Long Wey、Tsung-Han Tsai)

審核日期

2007-7-17

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