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姓名	吳孟哲(Meng-Jhe Wu)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	寬頻操作為基礎之靜態相位誤差校正延遲鎖定迴路 (Delay-Locked Loop with Static Phase Error Calibration Based on Wide-Range Operation)
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摘要(中)	隨著CMOS製程技術的進步，追求高頻時代也來臨了。以往都是使用鎖相迴路來當作系統中晶片之間的同步電路。但是鎖相迴路的電壓控制振盪器會有抖動累積問題。因此在這邊我們使用延遲鎖定迴路與頻率倍頻器來達到所需的高頻訊號。 本論文實現了一個以寬頻操作為基礎之靜態相位誤差校正延遲鎖定迴路，其中寬頻操作是使用多頻段電壓控制延遲線來完成，多頻段電壓控制延遲線是修改餓電流式延遲線並利用頻率偵測器偵測輸入頻率來切換頻段。 在靜態相位誤差校正方面，因為相位偵測器的相位偵測死帶(dead zone)與充放電幫浦的充放電不匹配(current mismatch)以及其它非理想效應會在延遲鎖定迴路鎖定時產生靜態相位誤差，此誤差會使得頻率倍頻器的抖動效能變差。在此篇論文提出的具偵測視窗之相位偵測器(Detect Window Phase Detector)可以用來校正靜態相位誤差。延遲鎖定迴路有鎖定範圍問題，也就是電壓控制延遲線之延遲時間必須在輸入時脈週期的0.5倍與1.5倍之間，否則會發生鎖定錯誤的狀況。因此在這裡也使用了一個自我校正電路來偵測電壓控制延遲線的訊號延遲多寡並防止鎖定錯誤的問題發生。 寬頻操作為基礎之靜態相位誤差校正延遲鎖定迴路是以CMOS 0.18um 1P6M製程進行設計跟模擬，電路操作電壓為1.8V，其輸出頻率範圍為25MHz~2.5GHz。而延遲鎖定迴路之輸入頻率範圍為25MHz~250MHz，輸入頻率在250MHz時鎖定時間為253ns，最大相位誤差校正改善前為3.57°，改善後為1.098°，消耗功率為10.1mW，此時輸出頻率為2.5GHz，峰對峰值的抖動量為22.6ps，晶片面積為0.466mm^2。
摘要(英)	To court high-frequency generation is coming with the evolution of CMOS process technology. The Phase-Locked Loop (PLL) was used for synchronous circuit between the system chips in the past. However, the voltage control oscillator have jitter accumulation problem in the PLL. Hence, Delay-Locked Loop (DLL) and frequency multiplier used to achieve the high frequency signal synchronization. DLL with static phase error calibration based on wide-range operation is proposed in this thesis. The wide-range operation is achieved in multi-band voltage controlled delay line . The multi-band voltage controlled delay line is modified current-starved delay line. It utilizes frequency detector that detect the input frequency to switch the delay line band. Due to dead zone of the phase detector, current mismatch of the charge pump and other non-ideally effect will cause the static phase error. The jitter performance of frequency multiplier will be worse. In order to solve the problems , the detect window phase detector is presented in thesis that is used to calibrate static phase error. DLL has a problem of locking range that is the delay time of voltage controlled delay line must between 0.5 times to 1.5 times for input clock period or it will occur the locking fault problem. Hence, we using a self-correct circuit to detect how long the delay time of the signal of voltage controlled delay line is. It also avoid the problem of locking fault. The proposed DLL with static phase error calibration is designed in CMOS 0.18um 1P6M process. The circuit is operate at 1.8V and the input frequency range is 25MHz~250MHz. Output frequency range is 25MHz~2.5GHz. The locking time is 253ns when the input frequency is 250MHz. Without the calibration, max phase error calibration of the proposed circuit is 3.57° and after the calibration is 1.098°.The power consumption is 10.1mW. The ten times output frequency is 2.5GHz and peak to peak jitter is 22.6ps. The core area of the chip is 0.466mm^2。
關鍵字(中)	★ 延遲鎖定迴路 ★ 頻率倍頻器 ★ 寬頻操作 ★ 靜態相位誤差校正	關鍵字(英)	★ Delay-Locked Loop ★ Frequency Multiplier ★ Wide Range Operation ★ Static Phase Error Calibration
論文目次	第一章緒論1 1.1 研究動機1 1.2 論文架構2 第二章傳統延遲鎖定迴路架構與理論3 2.1 延遲鎖定迴路架構介紹3 2.1.1 相位偵測器(Phase Detector)4 2.1.2 充電幫浦(Charge Pump)與迴路濾波器(Loop Filter)5 2.1.3 電壓控制延遲線(Voltage Control Delay Line)6 (A)RC時間常數控制之延遲元件7 (B)可變電容式之延遲元件7 (C)餓電流(Current-Starved)控制之延遲元件8 (D)差動對稱性負載之延遲元件9 2.2 延遲鎖定迴路理論分析10 2.2.1 鎖定範圍10 (A)諧波錯誤鎖定(Harmonic Locking)12 (B)阻塞錯誤鎖定(Stuck Locking)13 2.2.2 延遲鎖定迴路穩定度分析13 2.2.3延遲鎖定迴路設計考量15 第三章多重相位之自我校正相位誤差電路18 3.1 多重相位之相位誤差理論分析18 3.1.1寄生基調18 3.1.2延遲誤差18 3.1.3靜態相位誤差19 3.2 相位誤差校正電路介紹20 3.2.1自我校正下之精確I/Q Matching20 3.2.2多相位偏差校正22 3.2.3偏移平均化之電壓控制延遲線23 3.2.4數位式自我校正延遲鎖定迴路24 第四章寬頻操作為基礎之靜態相位誤差校正延遲鎖定迴路26 4.1 介紹26 4.2 電路架構與系統分析26 4.3 電路設計30 4.3.1 相位偵測器(Phase Detector)30 4.3.2 充放電幫浦(Charge Pump)與迴路濾波器(Loop Filter)31 4.3.3 多頻段電壓控制延遲線(Multi-Band Voltage Control Delay Line)34 4.3.4 頻率偵測器(Frequency Detector)37 4.3.5 自我修正(Self_Correct)電路37 4.3.6 具偵測視窗之相位偵測器(Detect Window Phase Detector)39 4.3.7 頻率倍頻器(Frequency Multiplier)40 第五章晶片實現與模擬44 5.1 模擬結果44 5.2 晶片佈局59 5.3 測試考量60 第六章結論61 6.1 結論61 6.2 未來改進方向61 參考文獻64
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指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2008-1-23
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