電子系統層級上之設計H.264編碼系統於單晶片網路系統平台

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姓名

林家宏(Chia-Hung Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

電子系統層級上之設計H.264編碼系統於單晶片網路系統平台
(An Electronic System Level Design of H.264 Encoding System on Network-on-Chip Platform)

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摘要(中)

隨著系統晶片日益複雜，複雜度不斷的增加，此時系統設計者必須找尋一種新的設計方法，而能夠去處理系統晶片的複雜度，且能縮短設計時程來提昇產品的生產率。一種明顯解決的方法則是提高設計的抽象層次。然而，對於系統設計者而言較關心的則是系統的架構、軟體/硬體的效能、以及通訊協定。因此，電子系統層級設計的方法能夠去滿足複雜的系統設計，且此方法能夠提高模擬的速度及幫助系統效能的估算。所以我們能夠反覆的分析系統架構及設計而不在是以一種架構來設計。
在這篇論文裡，我們以SystemC語言在交易層(Transaction-Level)的抽象層次來完成網路晶片(Network-on-Chip)平台。此網路晶片平台基本模組包含了:五個方向的交換器、傳輸鏈結、以及各式各樣的週邊模組。我們除了完成系統網路晶片平台外，我們亦完成一個H.264影像編碼器來當系統的平台應用，且以電子系統層級的設計方法去設計網路晶片平台的模組、設計空間的勘查方面的工作、及對系統效能做評估。我們依該方法在循序可執行程式碼和暫存器傳輸層級間建立抽象模型。讓我們可以在短時間之內評估系統的效能並且萃取重要的資訊以及能在設計過程中比較直覺的完成設計。
最後，整個網路晶片系統平台能夠模擬且驗證應用系統的功能正確性以及在傳輸鏈結上萃取動態的資訊，來分析解決系統的瓶頸所在。

摘要(英)

With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle the complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers care about are system architectures, Hardware/Software (HW/SW) performance, and the communication protocols. Furthermore, the electronic system level (ESL) design methodology can satisfy the requests on complex design with relative high simulation speed well performance evaluation. We can use it in the iterative design process rather than just in the early system architecting phase.
In this thesis, we implement a transaction level model (TLM) Network-on-Chip platform with SystemC. The basic modules: variable wrapper, 5-ports switch, transmission link and heterogeneous peripherals. In addition to NoC platform, we also implement the H.264 encoder as the system application, and apply a design methodology at ESL to do design modeling, design space exploration and performance evaluation. We base on it to establish abstract model between the sequential executable codes and the register transfer level (RTL) description. We are able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively.
Finally, the NoC platform will run the whole system simulation to verify the functional model and collect the dynamic information on the transmission link and IPs to analysis the bottle-neck of the system.

關鍵字(中)

★ 單晶片網路
★ 交易層級
★ 電子系統層級

關鍵字(英)

★ NoC
★ TLM
★ H.264
★ SystemC
★ ESL

論文目次

摘要----------------------------------------------------i
ABSTRACT------------------------------------------------ii
LIST OF FIGURE------------------------------------------vii
LIST OF TABLES------------------------------------------x
CHAPTER 1 INTRODUCTION---------------------------------1
1.1 MOTIVATION-------------------------------------1
1.2 CONTRIBUTION-----------------------------------6
1.3 THESIS ORGANIZATION----------------------------6
CHAPTER 2 SYSTEMC LANGUAGE OVERVIEW--------------------8
2.1 SYSTEMC FEATURES-------------------------------9
2.2 MODULES AND PROCESSES--------------------------10
2.3 INTERFACES, PORTS AND CHANNELS-----------------12
2.3.1 INTERFACES-------------------------------------13
2.3.2 PORTS------------------------------------------13
2.3.3 CHANNELS---------------------------------------14
2.4 SYNCHRONIZATION--------------------------------15
2.5 TIMING-----------------------------------------16
2.6 HARDWARE-ORIENTED DATA TYPE--------------------16
CHAPTER 3 TRANSACTION LEVEL MODELING-------------------17
3.1 ACCURACY MODEL OF TLM--------------------------17
3.2 TLM FOR ARCHITECTURE EXPLORATION---------------19
CHAPTER 4 INTRODUCTION OF THE NOC----------------------24
4.1 ARCHITECTURES OF THE NOC-----------------------24
4.2 COMMUNICATION PROTOCOLS------------------------27
4.3 COMPONENTS OF THE NOC--------------------------30
4.3.1 SWITCH-----------------------------------------30
4.3.2 Network Interface------------------------------31
CHAPTER 5 H.264 ENCODER SYSTEM-------------------------33
5.1 INTRODUCTION-----------------------------------33
5.2 INTRA PREDICTION-------------------------------35
5.3 TRANSFORM AND QUANTIZATION---------------------37
5.4 CONTEXT-BASED ADAPTIVE VARIABLE LENGTH CODING--40
5.5 INTER PREDICTION-------------------------------43
5.6 IN-LOOP DEBLOCKING FILTER----------------------45
CHAPTER 6 IMPLEMENTATION-------------------------------48
6.1 DESIGN ENVIRONMENT-----------------------------48
6.2 NETWORK-ON-CHIP PLATFORM-----------------------50
6.2.1 FLIT FORMAT DEFINITION IN SYSTEMC--------------51
6.2.2 DEVELOPING A SWITCH MODEL----------------------53
6.2.3 DEVELOPING A TRANSMISSION LINK MODELING--------55
6.3 ANALYSIS MODELING------------------------------60
6.3.1 CHANGE THE MASTER PORT INTERFACE---------------61
6.3.2 CHANGE THE SLAVE PORT INTERFACE----------------62
6.3.3 INITIALIZE THE MASTER DEVICES------------------63
6.3.4 INITIALIZE THE SLAVE DEVICES-------------------64
6.3.5 ANALYZE TRANSACTIONS---------------------------65
6.3.6 ANALYZE CONTENTION-----------------------------66
6.3.7 ANALYZE LATENCIES------------------------------67
6.4 H.264 ENCODER MODULE IN SYSTEMC----------------68
6.5 HDL PROXY MODULE-------------------------------73
CHAPTER 7 EXPERIMENT RESULTS---------------------------76
7.1 EXPERIMENT ENVIRONMENT-------------------------76
7.2 VERIFICATION AND ANALYSIS----------------------79
7.2.1 FUNCTIONAL VERIFICATION------------------------80
7.2.2 PLATFORM ANALYSIS------------------------------84
7.3 SYSTEMC/RTL CO-SIMULATION----------------------86
CHAPTER 8 CONCLUSION AND FUTURE WORK-------------------89
8.1 CONCLUSION-------------------------------------89
8.2 FUTURE WORK------------------------------------90
REFERENCES----------------------------------------------91
APPENDIX------------------------------------------------94

參考文獻

[1] T. Grötker, S. Liao, G. Martin and S. Swan,
System Design with SystemC, Kluwer Academic
Publishers, 2002.
[2] SystemC website. [Online]. Available:
http://www.systemc.org/
[3] Al Bobik, Handbook of Image and Video Processing
Compression Standards, Algorithms and
Architectures, Kluwer Academic Publishers, 2000.
[4] Analysis Manual, CoWare, 2006.
[5] S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell,
M. Millberg, J. Oberg, K. Tiensyrja, and A.
Hemani, “A Network on Chip Architecture and
Design Methodology,” in Proc. ISVLSI, 2002, pp.
105-112.
[6] Platform Architect v2005.2.2 Manual, CoWare, 2006.
[7] A. Agrawal and N. Gupta, “Architecture Oriented
Performance Optimizations for Bus Based System-on-
Chip Designs Using TLM,” CoWare, Inc. Tech. Rep.
2005.
[8] L.Benini, G. De Micheli, “Networks on chip: a
new paradigm for system on chip design”, Design,
Automation and Test in Europe conference, 2002.
[9] Wayne Wolf, Burak Ozer, and Tiehan Lv, “Smart
cameras for embedded systems, “ IEEE computer,
35(9), September 2002, pp. 48-53.
[10] K. Keutzer, S. Malik, A. Newton, J. Rabaey
and A.Sangiovanni-Vincentelli, "System Level
Design: Orthogonolization of Concerns and
Platform-Based Design”, IEEE Trans, on Computer-
Aided Design of Integrated Circuits and Systems
19, 12 (Dec. 2000).
[11] A Hemani, A. Jantsch, S. Kumar, A. Postula, J.
Oberg, M. Millberg, and D. Lindqvist, “Network
on Chip: An architecture for billion transistor
era”, Proc. Of the IEEE NorChip Conference, Nov.
2000.
[12] A. Jantsch, J. Soininen, M. Forsell, L. Zheng, S.
Kumar, M. Millberg, and J.Oberg, “Networks on
Chip”, Workshop at the European Solid State
Circuits Conference, Sep. 2001.
[13] F. Catthoor, D. Verkest, and E. Brockmeyer,
“Proposal for unified system design meta flow in
task-level and instruction-level design
technology research for multi-media
applications”, Proc. 11th Int. Symp. on System
Synthesis, 1998, 89,95.
[14] Yi-Ran Sun, “Simulation and Performance
Evaluation for Network on Chip”, MSc thesis,
Dept. of Microelectronics and Information
Technology, Royal Institute of Technology,
Stockholm.
[15] M. Forsell and S. Kumar, Virtual Distributed
Shared Memory for Network on Chip, Proc. of the
19th IEEE NORCHIP Conference, Nov. 12-31, 2001,
Kista.
[16] D. Bertozzi, S. Murali, R. Tamhanker, S.
Stergiou, L. Benini, and G. De Micheli. NoC
synthesis flow for customized domain specific
multiprocessor system-on-chip. IEEE Trans. On
Parallel and Dist. Systems,, 16(2):113-129, 2005.
[17] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny.
Cost considerations in network on chip.
Integration, Special Issue on NoC, 38(1):19-42,
Oct. 2004.
[18] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny.
QNoC: QoS architecture and design process for
network on chip. J. Systems Architecture, 50(2-
3):105-128, Feb. 2004.
[19] D. Bertozzi and L. Benini. Xpipes: a network-on-
chip architecture for gigascale systems-on-chip.
IEEE Circuit and Systems Magazine, 4:18-31, 2004.
[20] P. Gureeier and A. Greiner. A generic
architecture for on-chip packet-switched
interconnections. In DATE, pages 250-256, Mar,
2000
[21] J. Henkel, W. Wolf, and S. Chakradhar. On-chip
networks: a scalable, communication-centric
embedded system design paradigm. In 17th
International Conference on VLSI Design, pages
845-851, Jan. 2004.
[22] A. Jalabert, S. Murali, L. Benini, G. De Micheli,
"XpipesCompiler: a tool for instantiating
application specific networks on chip”, Design,
Automation and Test in Europe Conference and
Exhibition, 2004.
[23] www.opencores.org
[24] www.opnet.com
[25] M. Forsell, “A scalable high-performance
computing solution for networks on chips”,
IEEE Micro, Volume:22, Issue:5, 2002.
[26] Vun, Nicholas and Nguyen, T N A. “Development of
H.264 Encoder for a DSP Based Embedded System”,
ISCE 2007. June. 2007. pp. 1-4

指導教授

蔡宗漢(Taung-Han Tsai)

審核日期

2008-1-21

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