高精準度且快速鎖定之任意責任週期之時脈同步電路

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陳濟祥(Chi-Hsiang Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高精準度且快速鎖定之任意責任週期之時脈同步電路
(A high precision fast locking arbitrary duty cycle clock synchronization circuit)

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摘要(中)

在系統晶片中，訊號同步電路扮演越來越重要的角色，鎖相迴路(Phase-Locked Loop, PLL)和延遲鎖定迴路(Delay-Locked Loop, DLL)被廣泛地運用在晶片設計裡，但是，此兩種電路在使用上需要考慮到幾個問題，第一，由於上述兩種電路屬於閉迴路系統，產生頻寬方面的問題，需要考慮電路穩定性的問題。第二，電路需要花數十到數百個時脈週期才能完成相位鎖定，在鎖定過程中需要較大的功率消耗，於是，同步複製延遲電路被設計出來，藉此改善上述的缺點。
傳統的同步複製延遲電路有三個主要的缺點，首先，電路的相位誤差會受到輸出負載改變的影響而加大。其次，輸入訊號的責任週期受到限制。最後，則是因為單位元件延遲時間太大導致電路的解析度不足。受到上述的缺點影響，導致傳統的同步延遲電路僅能應用在記憶體模組。
本論文提出一高精準度且快速鎖定之任意責任週期之時脈同步電路，不僅擁有同步複製延遲電路的優點:快速鎖定與低功率消耗，並且輸入與輸出訊號間之相位誤差≦29 ps，輸入訊號的責任可以任意調變(25%~75%)，此外，相位誤差不會因為輸出負載的改變而增加。並以TSMC 0.13μm CMOS製程實現晶片，供應電壓為1.2V，操作在最高頻率600MHz時的功率消耗為2.4mW。核心電路的面積(不含I/O PAD)為0.039mm2 ，輸出訊號之最大抖動量(peak-to-peak jitter)為25.2 ps。在論文的後半段會有量測結果，以證明提出的新電路確實改善了上述的缺點。

摘要(英)

Clock synchronization plays a important role in designing VLSI circuit. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems in order to suppress the clock skew. However, these circuits have to consider some problems in using. First, PLL and DLL have issues of bandwidth because they are both closed loop systems. For this reason, they need to consider the stability of circuits. Second, they consume a lot of power in the process of locking. Consequently, the synchronous mirror delay circuit (SMD) was developed to improve the drawbacks.
However, there are some drawbacks in conventional SMD. First, the phase error will increase because of the output loading. Next, the duty cycle of input signal is limited. Finally, the poor resolution is due to the delay cell. These shortcomings will limit the application of the SMD.
A high precision fast locking arbitrary duty cycle clock synchronization circuit is proposed in the thesis, which not only keeps the advantage of SMD but the phase error between the input signal and output signal is less than 29 ps (simulated). And the tuning range of input signal’s duty cycle is 25% ~75%. Furthermore, the static phase error will not increase as the output loading changes. The test chip is fabricated in a 0.13-μm CMOS process and the supply voltage is 1.2V. It consumes 2.4mW when the operating frequency is 600MHz. The active area (without I/O PAD) is 0.039 mm2 , and the peak-to-peak jitter is 25.2 ps. There will be experimental results in latter half component of the thesis, which confirms the proposed circuit has improved certainly the drawbacks of SMD.

關鍵字(中)

★ 快速鎖定
★ 任意責任週期
★ 時脈同步

關鍵字(英)

★ fast locking
★ arbitrary duty cycle
★ clock synchronization

論文目次

摘要 ………………………………………………………………I
Abstract …………………………………………………………Ⅱ
目錄……………………………………………………………… Ⅲ
圖目錄 ……………………………………………………………V
表目錄………………………………………………………………VII
第1章緒論 1
1.1 研究動機 1
1.2 研究目的及用途 3
1.3 論文架構 4
第2章相關電路的分析 5
2.1 同步複製延遲電路 5
2.2 傳統式同步複製延遲電路 7
2.3 插入式同步複製延遲電路 9
2.4 省面積的插入式同步複製延遲電路 11
2.5 直接誤差偵測型同步複製延遲電路 13
2.6 混合式同步複製延遲電路 14
2.7 逐步近似式同步複製延遲電路 15
2.8 任意責任週期之同步複製延遲電路 17
2.9 電路特性比較 18
第3章高精準度且快速鎖定之任意責任週期之時脈同步電路 19
3.1 設計概念 19
3.2 電路架構及操作 20
3.3 粗調延遲電路 21
3.3.1 邊緣偵測器 23
3.3.2 量測延遲電路及改良式複製控制電路 24
3.3.3 可調延遲電路 25
3.4 細調延遲電路 26
3.4.1 細微延遲電路 27
3.4.2 相位比較器 28
3.4.3 逐漸近似暫存器 29
3.5 電路的操作頻率 30
第4章電路的模擬與量測 32
4.1 簡介 32
4.2 子電路之模擬 32
4.2.1 D型正反器 32
4.2.2 改良式複製控制電路 33
4.2.3 相位比較器 36
4.2.4 逐漸近似暫存器 38
4.3 新型時脈同步電路之特性分析 40
4.3.1 輸出負載的影響 40
4.3.2 輸入訊號的責任週期 41
4.3.3 操作頻率及精確度 42
4.4 實驗晶片之量測 46
4.5 量測結果 48
4.6 總結 52
第5章結論 53
5.1 結論 53
5.2 未來改進的方向 55
參考文獻 56

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2008-11-28

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