0.5-V 1.25-GHz 鎖相迴路之設計與實現

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姓名

黃瀞萱(Jing-Shiuan Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

0.5-V 1.25-GHz 鎖相迴路之設計與實現
(A 0.5-V 1.25-GHz Phase-Locked Loop)

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摘要(中)

由於近年環保意識的提升，加上可攜式無線通訊電子產品需求量的增加，因此在電路設計上，為了達到節約能源並延長電池壽命的目的，最簡單且直接的做法便是降低操作電壓。而且為了減少手持式電子產品上電池系統所佔的體積及重量，太陽能電池是目前最符合需求的低汙染能源，不但能減少發電過程中溫室效應氣體的排放，而且在光照充足的地區就能得到持續的供電，而一個太陽能電池所能供應的電壓約只有0.5-V，因此我們設計了一個能操作在供應電壓為0.5-V的鎖相迴路。
鎖相迴路是通訊系統中用來產生同步時脈的重要電路之一，因此也不能忽略鎖相迴路的功率消耗。在本論文中提出的鎖相迴路可以操作在0.5-V的低電壓，並輸出1.25-GHz八個相位的頻率，以達到高頻低功率的目的。此鎖相迴路使用改良式的閘極控制充放電幫浦，其不但能在低電壓下操作，並且能抑制傳統閘極控制充放電幫浦的漏電流。電壓控制振盪器部分使用多頻帶式基極驅動電壓控制振盪器，多頻帶的設計可降低其KVCO以減少電壓雜訊對輸出抖動的影響，且鎖相迴路可以在製程、電壓及溫度變異下仍鎖定在1.25-GHz的輸出頻率，此外基極驅動式的電壓控制振盪器比起傳統架構的電壓控制振盪器擁有較佳的線性度。本晶片以UMC 90nm 1P9M standard CMOS with RVT devices製程實現，當輸出頻率為1.25-GHz時，功率消耗為1.59 mW，其輸出的抖動為33.33 ps (p-p)，晶片的核心部分面積為0.074 mm2。

摘要(英)

In recent years, environmental protect issue has became more and more important. With the requirement on the portable wireless communication equipment increasing, the supply voltage should be downscaled to reduce power consumption and increase the lifetime of batteries. To reduce the cumbersome battery system and save energy, solar cell is popular green energy source and useful for supplying energy in portable electric products. Because that the voltage of a solar cell supplying is about 0.5V, we design a PLL with 0.5-V supply voltage.
Being a major block in a communication system, the power consumption of the PLL is not able to neglect. A 0.5-V 1.25-GHz 8-phase phase-locked loop (PLL) is proposed to achieve high output frequency and low power consumption. The proposed charge pump (CP) circuit has advantage of operating at low supply voltage and reducing the leakage current. The proposed bulk-driven voltage control oscillator (VCO) with digital-to-analog converter has advantage of operating at low supply voltage with using the bulk-controlled technique. The VCO use multi-band technique to degrade the KVCO, so that the noise effect would be reduced. Moreover, the VCO can lock at 1.25GHz output frequency with the process, voltage, and temperature (PVT) variation. The delay cell of VCO has higher linearity than the conventional delay cell by using bulk-controlled technique. The test chip is implemented in UMC 90nm 1P9M standard CMOS with RVT devices process. The output jitter performance of the proposed PLL is 33.33 ps (p-p) at 1.25- GHz. The power consumption of the PLL is 1.59 mW at 1.25-GHz and the core area is 0.074 mm2.

關鍵字(中)

★ 低電壓
★ 基極驅動
★ 0.5V
★ 鎖相迴路

關鍵字(英)

★ 0.5V
★ PLL
★ low voltage
★ bulk-driven

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第1章緒論 1
1.1 動機 1
1.2 低電壓鎖相迴路簡介及挑戰 2
1.3 論文組織 4
第2章鎖相迴路基本觀念 5
2.1 鎖相迴路操作原理及組成元件 5
2.1.1 相位頻率偵測器(Phase Frequency Detector, PFD) 6
2.1.2 充放電幫浦(Charge Pump, CP) 11
2.1.3 迴路濾波器(Loop Filter / Low Pass Filter, LPF) 13
2.1.4 電壓控制振盪器(Voltage Control Oscillator, VCO) 14
2.1.5 除頻器(Frequency Divider, FD) 18
2.2 鎖相迴路的迴路分析 19
2.2.1 公式推導 19
2.2.2 Matlab模擬 24
2.3 低電壓多頻帶電壓控制振盪器的頻帶分析 26
2.3.1 電壓控制振盪器的頻帶重疊分析 26
2.3.2 電壓控制振盪器的頻帶數最佳化 28
第3章低電壓電路設計技巧 31
3.1 常用的低電壓設計技巧及比較 32
3.1.1 基板控制技術(Bulk-controlled technique) 32
3.1.2 次臨界操作(Sub-threshold operation) 33
3.1.3 浮閘電晶體(Floating gate MOSFET) 34
3.1.4 自我疊接架構(Self-cascode structure) 35
3.1.5 位準轉換器(Level shifter approach) 37
3.1.6 各種低電壓設計技巧的比較 38
3.2 基板控制技術 39
3.3 基板漏電的影響及分析 44
第4章低電壓鎖相迴路的設計與製作 48
4.1 低操作電壓鎖相迴路的組成元件 48
4.1.1 相位頻率偵測器 48
4.1.2 充放電幫浦 52
4.1.3 迴路濾波器 55
4.1.4 多頻帶式基極驅動電壓控制振盪器 56
4.1.5 除頻器 66
4.2 低電壓鎖相迴路的模擬結果 68
第5章佈局及量測 74
5.1 鎖相迴路電路佈局 74
5.2 晶片量測 76
第6章結論 82
6.1 結論 82
參考文獻 83

參考文獻

[1]S.S. Rajput and S.S. Jamuar, “Low Voltage Analog Circuit Design Techniques,” IEEE Circuits and Systems Magazine, vol. 2, pp.24-42, 2002.
[2]S. Chatterjee, K. P. Pun, N. Stanic, Y. Tsividis and P. Kinget, “Analog Circuit Design Techniques at 0.5V,” Springer International Edition, 2006.
[3]T. Sakurai, “Low Power Digital Circuit Design,” IEEE European Solid-State Circuits Conference, pp. 11 – 18, Sept. 2004.
[4]J.G.. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
[5]W. Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 545-548, Jun. 1999.
[6]“An Analysis and Performance Evaluation of a Passive Filter Design Techniques for Charge Pump PLL’s,” National Semiconductor application note, July 2001.
[7]A.M. Samuel and J.P. Gyvez, “A Multi-Band Single-Loop PLL Frequency Synthesizer with Dynamically-Controlled Switched Tuning VCO,” IEEE Midwest Symposium on Circuits and Systems, pp.818-821, 2000.
[8]C. Tai, J. Lai and R. Chen, “Using Bulk-driven Technology Operate in Subthreshold Region to Design a Low Voltage and Low Current Operational Amplifier,” IEEE International Symposium on Consumer Electronics, pp.1-5, 2006.
[9]B.C. Paul, A. Raychowdhury and K. Roy, “Device Optimization for Digital Subthreshold Logic Operation,” IEEE Transactions on Electron Devices, vol. 52, pp.237-247, Feb. 2005.
[10]S. Yan, and E. Sanchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A Tutorial,” IEICE Trans. Fundamentals, vol. E83, No. 2, Feb. 2000.
[11]A. Veeravalli, E. Sanchez-Sinencio and J. Silva-Martinez, “Different Operational Transconductance Amplifier Topologies for Obtaining Very Small Transconductances,” IEEE International Symposium on Circuits and Systems, vol. 4, pp.189-192, May 2000.
[12] S. Kerthikeyan, S. Mortezapour, A. Tammineedi and E. Lee, “Low-Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 176-184, Mar. 2000.
[13]K. Arnim, E. Borinski, P. Seegebrecht, H. Fiedler, R. Brederlow, R. Thewes, J. Berthold and C. Pacha, “Efficiency of Body Biasing in 90-nm CMOS for Low-Power Digital Circuits,” IEEE J. Solid-State Circuits, vol. 39, pp. 42-48, Jul. 2004.
[14]W. Sansen, “Analog Design Challenges in Nanometer CMOS Technologies,” IEEE Asian Solid-State Circuits Conference, pp. 5-9, Nov. 2007.
[15]S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekher, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar and V. De, ”Ultra-Low Voltage Circuits and Processor in 180nm to 90nm Technolngies with a Swapped-Body Biasing Technique,” IEEE International Solid-State Circuits Conference, pp.156-157, Feb. 2004.
[16]M. Sumita, S. Sakiyama, M. Kinoshita, Y. Araki, Y. Ikeda and K. Fukuoka, “Mixed Body Bias Techniques with Fixed Vt and Ids Generation Circuits,” IEEE J. Solid-State Circuits, volume 40, pp.60-66, Jan. 2005.
[17]H. Ananthan, C.H. Kim and K. Roy, “Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS,” International Symposium on Low Power Electronics and Design, pp.8-13, 2004.
[18]H. Yu, Y. Inoue and Y. Han, “A New High-Speed Low-Voltage Charge Pump for PLL Applications,” International Conference on ASIC, vol. 1, pp. 387-390, Oct. 2005.
[19]M. El-Hage and F. Yuan, “An Overview of Low-Voltage VCO Delay Cells and A Worst-Case Analysis of Supply Noise Sensitivity,” Electrical and Computer Engineering, vol. 3, pp. 1785-1788, May 2004.
[20]M. Mansur and C. Yang, “A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation.” IEEE J. Solid-State Circuits, vol. 38, pp. 1804-1812, Jul. 2003.
[21]I. Hwang, C. Kim and S. Kang, “A CMOS Self-Regulating VCO With Low Supply Sensitivity,” IEEE J. Solid-State Circuits, vol. 40, pp. 1549-1556, Jul. 2004.
[22]W. Jung, H. Choi, C. Jeong, K. Kim, W. Kim, H. Jeon, G. Koo, J. Kim, J. Seo, M. Ko and J. Kim, “A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to Current Converter,” IEEE International Solid-State Circuits Conference, pp. 310-311, Feb. 2007.
[23]Y. Lo, “Design and Implementation of CMOS High-Performance Low-Voltage Clock Synchronization Circuits,” PhD thesis, Dept. of Electrical Eng., National Central University, Chungli, Taiwan, 2008.
[24]L. Sun and D. Nelson, “A 1V GHz Range 0.13um CMOS Frequency Synthesizer,” IEEE Custom Integrated Circuits Conference, pp. 327-330, May 2001.
[25]J. Nakanishi, H. Notani, H. Makino and H. Shinohara, “A Wide Lock-in Range PLL using Self-Calibrating Technique for Processors,” IEEE Asian Solid-State Circuits Conference, pp.285-288, Nov. 2005.
[26]J. Navarro and W. Noije, “A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),” IEEE J. Solid-State Circuits, vol. 34, pp. 97-102, Jan. 1999.
[27]P. Raha, “A 0.6-1.2V Low-Power Configurable PLL Architecture for 6GHz-300MHz Applications in a 90nm CMOS Process,” IEEE VLSI Symposium, pp. 232-235, Jun. 2004.
[28]H. Hsieh, C. Lu and L. Lu, “A 0.5-V 1.9GHz Low-Power Phase-Locked Loop in 0.18-um CMOS,” IEEE VLSI Symposium, pp.164-165, Jun. 2007.
[29]S. Yu and P. Kinget, “A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 304-306, Feb. 2007.
[30]X. Yu, Y. Sun, L. Zhang, W. Rhee and Z. Wang, “A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering,” IEEE International Solid-State Circuits Conference, pp. 346-348, Feb. 2008.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2008-11-28

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