應用於生理訊號量測系統之截波穩定型類比前端電路

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林威志(Wei-Chih Lin) 查詢紙本館藏

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電機工程學系

論文名稱

應用於生理訊號量測系統之截波穩定型類比前端電路
(An Analog Front-End Circuit for Bio-signal Measurement System Using Chopper Stabilization Technique)

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摘要(中)

近幾年來不同生醫應用層面的植入式生理訊號量測系統發展趨向於微小化並搭配無線方式傳輸訊號。以整體系統來看，從電極端接收的生理訊號極為微弱，為了完整地記錄生理訊號，其電路設計上朝向低雜訊、高解析度、低功率消耗等特點邁進。
本篇主旨為提出一應用於生醫訊號量測系統之全差動對稱式類比前端電路，可針對極微弱的神經電圖(Electromyography, ENG)訊號作一記錄。為了將其中低頻的非理想成份諸如閃爍雜訊、直流偏移電壓等消除，提高其訊號雜訊比，以增加記錄的神經訊號的可辨度，本電路中放大級採用截波穩定型的技術。再者，為了降低整體電路的功率消耗，將輸入級的場效電晶體操作於弱反轉區。而截波穩定型放大器當中的帶通濾波器使用不同於一般濾波器的實現方式完成。本文提出架構由差動差分放大器與米勒積分器所構成，此架構可將從電極與電解溶液介面而產生的直流偏移電壓消除。
本文所提整體類比前端電路包含偏壓電路、時脈產生器、截波穩定型放大器、後置放大器、和二階連續時間低通濾波器。在電路實現上，在有效頻寬約9.3 KHz下，其直流電壓增益達到62.9 dB、總等效輸入相關雜訊電壓約為7.05 μVrms、其有效位元數達到10位元的解析度。使用台積電0.18 μm 標準CMOS 1P6M製程完成，其晶片面積為0.88 x 0.43 mm2。在1.8 V電源供應下，總功率消耗約為230 μW。

摘要(英)

In recent years, the implanted bio-signal measurement devices for various bio-medical applications tend to be minimized and with wireless transmission capabilities. Since physiological signals from electrodes are very tiny and are difficult to be recorded, design of the bio-signal analog-front-end circuits are always with the features of low-noise, high resolution, and low power consumption.
This work presents a fully differential and analog-front-end circuit for bio-signal measurement system that can be used to record the very tiny electroneurography (ENG) signals. Chopper stabilization technique (CHS) is employed in the amplification stage to eliminate the non-ideal low-frequency effects, such as the flicker noise and the DC-offset voltage. It improves the signal-to-noise ratio (SNR) and offers a higher resolution for the recorded neuron signals. In order to decrease the power dissipation of the system, input stages of field-effect transistors are designed to be operating at the weak-inversion region. In addition, the band-pass filter of the chopper-stabilized amplifier consists of a differential difference amplifier and a Miller integrator, which are different to the traditional design with passive resistors and capacitors. The purpose of this BPF is aimed to cancel out the DC-offset voltage from the electrode-electrolyte interface.
The whole AFE circuit includes a bias circuit, a clock generator, a chopper stabilization amplifier, a post-amplifier, and a second-order continues-time low-pass filter. Such AFE circuit is implemented in the TSMC 0.18-μm one-poly six-metals CMOS process and provides a mid-band gain of 62.9 dB, a signal bandwidth approximates up to 9.3 KHz, a total equivalent input-referred noise of about 7.05 μVrms, and a 10-bit resolution. Supplied at 1.8 V, the proposed AFE circuit consumes around 230 μW. The chip area is 0.88 × 0.43 mm2.

關鍵字(中)

★ 米勒積分器
★ 差動差分放大器
★ 截波穩定
★ 類比前端

關鍵字(英)

★ differential difference amplifier
★ miller integrator
★ analog front-end
★ chopper stabilization

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 ix
第一章緒論 1
1.1 背景 1
1.2 研究動機 3
1.3 論文架構 4
第二章類比前端電路設計考量 5
2.1 生理訊號類別 5
2.2 生醫電位電極之等效模型 7
2.3 設計考量 9
第三章雜訊源和殘餘偏壓現象探究與截波穩定技術理論分析 12
3.1 雜訊源 12
3.1.1 熱雜訊 (Thermal Noise) 13
3.1.2 閃爍雜訊 (Flicker Noise) 15
3.2 殘餘偏壓現象 16
3.2.1 通道電荷注入 (Channel Charge Injection) 17
3.2.2 時脈饋入 (Clock Feedthrough) 18
3.3 電荷注入抵消 19
3.3.1 模仿(dummy)元件 19
3.3.2 互補式開關(Complementary Switches) 21
3.3.3 差動電路架構 22
3.4 截波穩定技術 (Chopper Stabilization Technique) 22
3.4.1 雜訊分析 27
3.4.2 殘餘偏壓分析 28
3.5 弱反轉區(weak inversion region)特性 32
第四章類比前端電路硬體架構 38
4.1 硬體架構簡介 38
4.2 時脈產生器 (Clock Generator) 39
4.3 調變器 (Modulator / Demodulator) 40
4.4 帶通濾波器 (Band-Pass Filter) 41
4.4.1 差動差分放大器 (Differential Difference Amplifier, DDA) 42
4.4.2 米勒積分器（Miller Integrator） 44
4.4.3 共模回授 (Common-Mode Feedback, CMFB) 48
4.4.4 帶通濾波器硬體電路 50
4.4.5 雜訊源分析 50
4.5 後置放大器 (Post Amplifier) 52
4.6 低通濾波器 (Low-Pass Filter) 53
4.7 主動式元件 59
4.8 類比前端電路 60
第五章類比前端電路實現與模擬結果 61
5.1 各運算放大器之模擬結果 61
5.2 類比前端電路之模擬結果 63
5.3 線性度模擬分析 65
5.4 製程與溫度偏移模擬 67
5.5 製程偏移討論與未來改進方式 68
5.6 雜訊模擬分析 69
5.7 總結與佈局說明 71
第六章結論 75
參考文獻 76
附錄 81

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2009-1-19

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