適用於平行處理及排程技術的無衝突定址法演算法之快速傅立葉轉換處理器設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：56

、訪客IP：3.144.25.74

姓名

林忠毅(Chung-yi Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於平行處理及排程技術的無衝突定址法演算法之快速傅立葉轉換處理器設計
(A Conflict-Free Memory Addressing Scheme For Fast Fourier Transform Processors With Parallelism And Scheduling Techniques)

相關論文

★ 具輸出級誤差消除機制之三位階三角積分D類放大器設計	★ 應用於無線感測網路之多模式低複雜度收發機設計
★ 用於數位D類放大器的高效能三角積分調變器設計	★ 交換電容式三角積分D類放大器電路設計
★ 適用於IEEE 802.11n之4×4多輸入多輸出偵測器設計	★ 應用於無線通訊系統之同質性可組態記憶體式快速傅立葉處理器
★ 3GPP LTE正交分頻多工存取下行傳輸之接收端細胞搜尋與同步的設計與實現	★ 應用於3GPP-LTE下行多天線接收系統高速行駛下之通道追蹤與等化
★ 適用於正交分頻多工系統多輸入多輸出訊號偵測之高吞吐量QR分解設計	★ 應用於室內極高速傳輸無線傳輸系統之設計與評估
★ 適用於3GPP LTE-A之渦輪解碼器硬體設計與實作	★ 下世代數位家庭之千兆級無線通訊系統
★ 協作式通訊於超寬頻通訊系統之設計	★ 適用於3GPP-LTE系統高行車速率基頻接收機之設計
★ 多使用者多輸入輸出前編碼演算法及關鍵組件設計	★ 無線感測網路之定位追蹤演算法設計與實作

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

近年來正交分頻多工系統(orthogonal frequency division multiplexing)通訊系統蓬勃發展，如digital video broadcasting-terrestrial (DVB-T)，handheld terminals (DVB-H)，3GPP long term evolution (3GPP-LTE)，ultra wide band (UWB)，802.16e/m和802.20等，快速傅立業轉換處理器是應用在正交分頻多工系統中重要的一塊電路。
本篇論文提出高基數快速傅立業轉換處理器結合多路徑延遲交換器架構與記憶體基底架構，利用管線式之多路徑延遲交換器架構其操作時脈可以小於或等於系統的操作頻率，減少快速傅立業轉換處理器的運算時間以降低功率消耗，而運用記憶體基底架構使用較少的蝴蝶運算器的優點來減少蝴蝶運算器數目。除此之外，提出一種快速傅立業轉換之無衝突定址方式來達到最小的記憶體需求與連續運算，並將複數乘法運算重新排程以提高複數乘法器的使用率來降低複數乘法器的數目，設計一個能運算Radix-2、Radix-22、Radix-23的混基數多路徑延遲交換器電路，使設計的可變長度快速傅立業轉換處理器可以運算64~4096點。使用TSMC 0.18μm CMOS製程實現1024點的快速傅立業轉換處理器，在30MHz的速度下功率消耗為70.5mW，晶片中心的尺寸為1.56*1.56mm2。

摘要(英)

Orthogonal frequency division multiplexing (OFDM) communication systems became popular in recent years, like digital video broadcasting-terrestrial (DVB-T), handheld terminals (DVB-H), 3GPP long term evolution (3GPP-LTE), ultra wide band (UWB), 802.16e/m and 802.20. In orthogonal frequency division multiplexing communication systems, a Fast Fourier transform (FFT) processor is an important kernel.
In this thesis, we proposed a high radix FFT processor that combines multi-path delay commutator architecture with memory-based architecture. By using pipelined multi-path delay commutator FFT architecture, the operation clock frequency can be set less than or equal to the system sampling rate and thus the power consumption can be reduced. We also take advantage of the memory-based architecture to save the number of butterfly units. Besides, a novel conflict-free memory addressing scheme is proposed to accomplish this continuous-flow FFT processor with the least requirement of the memory. We also schedule the complex multiplication to reduce the required complex multipliers and increase their utilization. A mixed-radix multi-path delay commutator is designed to calculate radix-2, radix22 and radix23 algorithm so that our proposed FFT processor can provide FFT computations from 64 to 4096 points. We have implemented the proposed FFT processor of 1024 points in TSMC 0.18μm CMOS technology. The power consumption is 70.5mW at 30-MHz operating frequency and 1.8-V supply voltage with core area of 1.56*1.56mm2.

關鍵字(中)

★ 快速傅立業轉換

關鍵字(英)

★ Fast Fourier Transform
★ FFT

論文目次

目錄
致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章緒論 1
1.1 正交分頻多工系統發展 1
1.2 研究動機 2
1.3 論文架構 3
第二章快速傅立葉轉換演算法 4
2.1 Radix-2演算法[7] 4
2.2 Radix-4/Radix-22演算法 8
2.3 Radix-8/ Radix-23演算法 10
第三章快速傅立業轉換處理器架構 12
3.1 單一路徑延遲回授架構 12
3.1.1 Radix-2單一路徑延遲回授架構 12
3.1.2 Radix-4/ Radix-22單一路徑延遲回授架構[9] 13
3.1.3 Radix-8/ Radix-23單一路徑延遲回授架構[9] 14
3.2 多路徑延遲交換器架構 15
3.2.1 Radix-2多路徑延遲交換器架構 16
3.2.2 Radix-4/Radix-22多路徑延遲交換器架構 16
3.2.3 Radix-8/Radix-23多路徑延遲交換器架構 17
3.3 記憶體基底架構 18
3.4 比較各種快速傅立業轉換處理器架構 19
第四章電路設計 22
4.1 基數選擇 22
4.2 多路徑延遲交換器記憶體基底電路 23
4.2.1 可連續運算快速傅立業轉換處理器 24
4.2.2 多路徑延遲交換器記憶體基底電路工作模式 26
4.2.3 混基數多路徑延遲交換器使用數目 28
4.3 混基數多路徑延遲交換器 29
4.3.1 Radix-2混基數多路徑延遲交換器 31
4.3.2 Radix-22混基數多路徑延遲交換器 32
4.3.3 Radix-23混基數多路徑延遲交換器 32
4.3.4 常數乘法器 33
4.4 可變長度快速傅立業轉換無衝突定址法 35
4.5 複數乘法運算排程 40
4.6 唯讀記憶體 45
4.7 分享旋轉因子電路 46
第五章電路實現與模擬結果 50
5.1 定點數模擬結果 50
5.2 晶片佈局設計 54
5.3 晶片佈局結果與規格 58
第六章結論 62
參考文獻 63

參考文獻

[1] Richard van Nee and Ramjee Prasad, “OFDM Wireless Multimedia Communications,” Artech House, 2000.
[2] IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems, Jan. 2006.
[3] Project IEEE 802.20 Working Group on Mobile Broadband Wireless Access.
http://ieee802.org/20/. Title MBFDD and MBTDD Wideband Mode: Technology Overview. Jun. 2006.
[4] Project IEEE 802.16 Broadband Wireless Access Working Group. http://ieee802.org/16/.
Title Draft IEEE 802.16m Evaluation Methodology Document. Mar. 2007.
[5] 3GPP TR 25.814 v7.1.0. ”Physical Layer Aspects for Evolved UTRA.” Sept. 2006.
[6] Pei-Yun Tsai, Tsung-Hsueh Lee and Tzi-Dar Chiueh, “Power-Efficient Continuous-Flow Memory-Based FFT Processor for WiMax OFDM Mode,” IEEE Intelligent Signal Processing and Communications, pp. 622-625, Dec. 2006.
[7] Alan V. Oppenheim , Ronald W. Schafer, and John R. Buck, “Discrete-Time Signal Processing,” Prentice Hall, 1989.
[8] Shousheng He and Mats Torlelson, “Designing Pipeline FFT Processor for OFDM (de)Modulation,” Proc. IEEE URSI International Symposium on Signal, Systems and Electronics, pp. 257-262, 1998.
[9] Y.-T. Lin, P.-Y. Tsai and T.-D. Chiueh, “Low-Power Variable-Length Fast Fourier Transform Processor,” IEE Proc.-Comput. Digit. Tech., vol. 152, no. 4, pp. 499-506, Jul. 2005.
[10] Ching-Hsien Chang, Chin-Liang Wang and Yu-Tai Chang, “A Novel Memory-Based FFT Processor for DMT/OFDM Applications,” IEEE Acoustics, Speech, and Signal Processing, vol. 4, pp. 1921-1924, Mar. 1999.
[11] Li, W., and Wanhammer, L.: “A pipeline FFT processor”. Proc. Workshop Signal Processing Systems Design and Implementation, pp. 654–662, 1999.
[12] R. Radhouane, P. Liu and C. Modlin, “Minimizing the Memory Requirement for Continuous Flow Mixed Mode FFT (CFMM-FFT),” IEEE International Symposium on Circuits and Systems, pp. 116-119, May. 2000.
[13] Byung G. Jo and Myung H. Sunwoo, “New Continuous- Flow Mixed-Radix (CFMR) FFT Processor Using Novel In-Place Strategy,” IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 52, no. 5, pp. 911-919, May. 2005.
[14] Bevan M. Baas, “A Low-Power, High-Performance, 1024-Point FFT Processor,” IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp. 380-387, Mar. 1999.
[15] Shuenn-Yuh Lee, Chia-Chyang Chen, Chyh-Chyang Lee and Chih-Jen Cheng, “A Low-Power VLSI Architecture for a Shared-Memory FFT Processor with a Mixed-Radix Algorithm and a Simple Memory Control Scheme,” IEEE International Symposium on Circuits and Systems, pp. 157-160, 2006.
[16] Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee, “A Dynamic Scaling FFT Processor for DVB-T Applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 2005-2013, Nov. 2004.
[17] Yutai Ma and Lars Wanhammar, “A Hardware Efficient Control of Memory Addresing for High-Performance FFT Processors,” IEEE Transactions on Signal Processing, vol. 48, no. 3, pp. 917-921, Mar. 2000.
[18] Lihong Jia, Yonghong Gao, Jouni Isoaho and Hannu Tenhunen, “A New VLSI-Oriented FFT algorithm and Implementation,” IEEE ASIC Conference, pp. 337-341, Sept. 1998.
[19] Yu-Wei Lin, Hsuan-Yu Liu, and Chen-Yi Lee, “A 1-GS/s FFT/IFFT Processor for UWB Applications,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1726-1735, Aug. 2005.
[20] Y. Chen, Y. W. Lin, and C. Y. Lee, “A Block Scaling FFT/IFFT Processor for WiMAX Applications,” IEEE ASSCC, pp. 203-206, Nov. 2006.
[21] Anthony T. Jacobson, Dean N. Truong, and Bevan M. Baas, “The Design of a Reconfigurable Continuous-Flow Mixed-Radix FFT Processor,” IEEE International Symposium on Circuits and Systems, pp. 1133-1136, May. 2009.
[22] Guichang Zhong, Fan Xu and Alan N. Willson, Jr, “A Power-Scalable Reconfigurable FFT/IFFT IC Based on a Multi-Processor Ring,” IEEE Journal of Solid-State Circuits, vol. 41, no. 2, pp. 483-495, Feb. 200

指導教授

蔡佩芸(Pei-yun Tsai)

審核日期

2009-7-15

推文