![]() |
|
以作者查詢圖書館館藏 、以作者查詢臺灣博碩士 、以作者查詢全國書目 、勘誤回報 、線上人數:17 、訪客IP:18.191.162.242
姓名 傅仁弘(Ren-Hong Fu) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 自動降低運算跨導放大器電路之製程變異敏感度的研究
(Automatic Process Sensitivity Reduction for OTA Circuits)相關論文 檔案 [Endnote RIS 格式]
[Bibtex 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
[下載]
- 本電子論文使用權限為同意立即開放。
- 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
- 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
摘要(中) 隨著製程技術的進步,製程變異對電路元件的影響也越來越大,造成設計良率不斷下降。為了解決這個問題,以設計為導向的良率改善(design-for-yield)技術是一個相當熱門的研究方向,在設計的流程中,導入製程變異對電路的影響,將製程變異對電路的影響降低。本論文提出一個自動降低電路的製程變異敏感度的方法,藉由分析電晶體(MOS)尺寸與製程變異敏感度之間的關係,來對運算跨導放大器(operational transconductance amplifier, OTA)電路進行自動元件尺寸調整,以降低其製程變異敏感度(process variation sensitivity)。整個流程以C語言實現。在電路效能不做太大的變動的前提下,透過退火演算法(simulated annealing),來對電路面積與製程變異敏感度做最佳化。從實驗結果觀察,本論文所提出的方法確實可以降低製程變異敏感度,進而提升設計良率。
摘要(英) With the advance process technology, process variation has more and more impacts on the device behaviors, which reduces the design yield dramatically. In order to solve this problem, design-for-yield (DFY) techniques are hot research topics recently. In the DFY design flow, the influence of process variation will be considered at early design stage to reduce the process variation impacts on the circuits. In this thesis, an automatic DFY approach is proposed for OTA circuits to reduce their process variation sensitivity. According to the relationship between transistor sizes and process variation sensitivity, the proposed flow automatically adjusts the transistor sizes to reduce process variation sensitivity of OTA circuits. This flow has been implemented by C language. With little changing on circuit performances, this program will find an optimal solution considering the process sensitivity and area overhead using simulated annealing algorithm. As shown in the experimental results, the proposed approach does reduce the process variation sensitivity and improve the design yield.
關鍵字(中) ★ 運算跨導放大器
★ 製程變異敏感度關鍵字(英) ★ OTA
★ process variation sensitivity論文目次 目 錄
摘 要 i
Abstract ii
誌 謝 iii
目 錄 iv
圖 目 錄 v
表 目 錄 vi
一、緒論 1
1-1 背景 1
1-2 類比電路最佳化與良率分析 2
1-3 研究動機 4
1-4 論文組織 5
二、背景知識 6
2-1 簡介 6
2-2 降低製程變異敏感度流程 6
2-3 摺疊疊接運算跨導放大器電路 7
2-4 退火演算法 8
三、電路製程變異敏感度分析 11
3-1 簡介 11
3-2 電晶體(MOS)分組 11
3-3 製程變異敏感度權重方程式 12
3-4 電路敏感度分析結果 15
四、自動降低製程變異敏感度的流程 18
4-1 簡介 18
4-2 有條件的電晶體(MOS)尺寸擾動 19
4-2-1 Power的擾動 20
4-2-2 Unit gain bandwidth的擾動 22
4-2-3 Gain的擾動 22
4-3 擾動代價 25
五、實驗結果 28
5.1 參數設定 28
5.2 實驗結果 29
5.3 擾動參數變動 33
5.4 電路規格變動 34
六、結論與未來研究方向 36
參考文獻 37
參考文獻 參考文獻
[1] A. Asenov, G. Slavcheva, Andrew R. Brown, John H. Davies, and S. Saini, “Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub-100 nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001
[2] E. Ochotta, R. Rutenbar, and L. R. Carley, “Synthesis of High-Performance Analog Circuits in ASTRX/ OBLX,” IEEE Trans. Computer-Aided Design, Mar. 1996
[3] G. Van der Plas, G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche, G. Gilen, W. Sansen, P. Veselinovic, and D. Leenaerts, “AMGIE- A Synethsis Environment for CMOS Analog Integrated Circuits,” IEEE Trans. Computer-Aided Design, Sept. 2001
[4] G. E. Gielen, H. Walscharts, W. Sansen, “Analog circuit design optimization based on symbolic simulation and simulated annealing,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 3, JUNE 1990
[5] H. Graeb, S. Zizala, J. Eckmmueller, K. Antreich. “The Sizing Rules Method for Analog Integrated Circuit Design,” Computer-Aided Design, 2001.
[6] R. Iskander, M. Dessouky, M. Aly, M. Magdy, N. Hassan, N. Soliman, and S. Moussa, “Synthesis of CMOS Analog Cells Using AMIGO,” Design, Automation and Test in Europe Conference and Exhibition, 2003
[7] Michael Pronath, “Circuit Design for Yield with MunEDA WiCkeD,” MunEDA Technical Forum Taiwan, 2008
[8] A. Seifi, K. Ponnambalam, and J. Vlach, “A unified approach to statistical design centering of integrated circuits with correlated parameters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 1, pp. 190–196, Jan. 1999.
[9] S. Kirkpatrick, C. D. Gelatt, Jr., M. P. Vecchi, “Optimization by Simulated Annealing,” Science, Vol. 220. no. 4598, pp. 671 – 680, May 1983
[10] P. R. Gray and R. G. Meyer, “Analog Integrated Circuits”, 3rd Ed., New York, Wiley, 1993.
[11] B. Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw Hill, 2001.
[12] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design”, OXFORD, 2rd Ed., 2002.
[13] Kirkpatrick, S.; C. D. Gelatt, M. P. Vecchi, "Optimization by Simulated Annealing". Science. New Series 220 (4598): 671-680.
[14] Franco Busetti, Simulated annealing overview, http://www.cs.ubbcluj.ro/~csatol/mestint/pdfs/Busetti_AnnealingIntro.pdf
[15] 趙晏廷, ”運算放大器之自動化設計流程及形為模型研究,”國立中央大學電機工程學系碩士論文, July, 2007
指導教授 劉建男(Chien-Nan Liu) 審核日期 2009-7-16 推文 plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
網路書籤 Google bookmarks
del.icio.us
hemidemi
myshare