| 摘要(英) |
As VLSI technology goes into nanometer era, the power integrity problem becomes one of the critical issues that limit the design performance. Traditionally, accurate supply current waveform can only be obtained from transistor-level simulation. Power integrity check is mostly performed at very late design stage in current design flow. Therefore, a high level current model for logic blocks using dynamic levelization algorithm is proposed to solve this problem. Proposed dynamic levelization algorithm can simplify the waveform complexity by grouping the gates by their logic level. Then, levelized current waveforms are transformed by DCT to obtain regular frequency domain waveforms. Thus, any shapes of current waveforms like triangular, trapezoidal, or multi-peak waveforms can be estimated by the proposed model without any manual tuning and extra information except the input/output values. Finally, the experimental results prove proposed that high-level current model provide accurate enough supply current waveforms for noise analysis at early design stages.
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| 參考文獻 |
﹝1﹞Rishi Bhooshan, Bindu P Rao, “ Optimum IR Drop Models for Estimation of Metal Resource Requirements for Power Distribution Network ”, IFIP International Conference on Very Large Scale Integration, pp. 292-295, Oct. 2007
﹝2﹞Amir H. Ajami, Kaustav Banerjee, Amit Mehrotra, Massoud Pedram, “ Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs ”, International Symposium on Quality Electronic Design, pp. 35-40, Mar. 2003
﹝3﹞Yu Zhong, Martin D. F. Wong, “ Fast Algorithms for IR Drop Analysis in Large Power Grid ”, Computer-Aided Design, pp. 351-357, Nov. 2005
﹝4﹞” Simultaneous Switching Noise and Signal Integrity “, 2006 Actel Corporation
﹝5﹞Jin Zhao, Qing-lun Chen, ” A New Methodology for Simultaneous Switching Noise Simulation ”, Electrical Performance of Electronic Packaging, pp. 155-158, Oct. 2000
﹝6﹞Sang Won Song, Mohammed Ismail, Gyu Moon, Dong Yong Kim, ” Accurate Modeling of Simultaneous Switching Noise in Low Voltage digital VLSI ”, International Symposium on Circuits and Systems, Vol. 6, May 1999
﹝7﹞Atsushi Nakamura, Jyunichi Mano, Tatsuya Nagata, Hiroya Shimizu,Masayoshi Yagyu, Kunihiko Nishi, Kanji Otsuka,” Handling of Mutual Inductance in Simulation of Simultaneous Switching Noise ”, Electronic Components and Technology Conference, pp.663-668, May 1994
﹝8﹞Anand Raghunathan, Iraj K.Jha, Sujit Dey, High-LEVEL POWER ANALYSIS AND OPTIMIZATION, 1998
﹝9﹞Srinivas Bodapati, and Farid N. Najm,” High-Level Current Macro Model for Logic Blocks ” , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 5, May 2006
﹝10﹞楊侑成, “High-Level Current Macro Model using Neural Network”, June 2006
﹝11﹞羅華強，類神經網路-MATLAB的應用，六版，清蔚科技，民國九十年
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