高性能展頻時脈產生器之設計

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曾暐盛(Wei-Sheng Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高性能展頻時脈產生器之設計
(Design of High Performance Spread Spectrum Clock Generator)

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摘要(中)

在現今電子裝置往高頻發展的同時，電磁干擾儼然已成為一不可忽視之問題。展頻時脈產生器被廣泛運用在解決電磁干擾的運用上。此篇論文研究兩種不同規格展頻時脈產生器之運用，一為0.5伏特之展頻時脈產生器，及6-GHz之展頻時脈產生器。此0.5伏特之展頻時脈產生器在超低功耗的規格下，達到1.5-GHz之SATA規格。6-GHz展頻時脈產生器則具有全差動式的構造，對於電源雜訊有較高的抵抗力，同時也達到SATA規格。
本論文以0.5伏特為目標電壓，提出順向基體偏壓的最佳化技巧-非對稱式順向基體偏壓與通道寬度最佳化，可以在達到更高操作速度的同時，還能減少功率的消耗並縮小晶片面積與成本。而相位切換式多模數除頻器，具有0.5個週期的解析度，能達到高速的操作。精度增強形差異績分調變器，利用低位元之累加器，等效為高位元之累加器，達到更小的量化誤差，並操作在更低頻率而節省功率。測試晶片實現在台積電1P8M 0.13製程，核心面積0.12um¬2，使用0.5伏特之供應電壓操作在1.5-GHz，其功率消耗僅1.4m瓦特。
差動式6-GHz展頻時脈產生器，符合未來第三代SATA之規格，其全差動式設計，大大減少迴路濾波器之面積與成本，並具有較強抵抗電源共模雜訊之能力。而修正式電流式邏輯除頻器，能夠根據控制電壓改變其可除頻率，獲得大的除頻範圍。測試晶片實現在台積電1P6M 0.18製程，核心面積0.11um¬2，使用1.8伏特之供應電壓操作在6-GHz，其功率消耗為34.9m瓦特。

摘要(英)

As frequency increasing in electrical devices, electromagnetic interference (EMI) becomes a serious problem. Spread spectrum clock generator (SSCG) is widely used to reduce EMI. There are two SSCG proposed in this thesis. One is a 0.5 V SSCG and the other is 6-GHz SSCG. The 0.5 V SSCG achieves serial advanced technology attachment (SATA) 1.5-GHz specification with very low power consumption. The 6-GHz SSCG has fully differential architecture, which immunizes common mode supply noise, and fits SATA specification.
The proposed asymmetry forward body bias with channel width scaling (AFBWS) is the optimization of forward body bias. This technique not only increases max operation speed, but also reduces power consumption and area. Phase switch multi-modular divider (PSMMD) can operate at high speed with half period of resolution. Accurate enhanced sigma delta modulator (AESDM) is as higher data width and simultaneously operates at lower frequency to save power. The test chip was fabricated in TSMC 0.13 1P8M process which core area is 0.12 um2. The power consumption at 1.5-GHz is only 1.4 mW with 0.5 V supply.
The 6-GHz SSCG fits the SATA specification. Its fully differential structure not only dramatically reduces LPF area and cost, but also immunizes common mode supply noise. The modified current mode divider can change its dividable range by control voltage. Thus, achieves larger input frequency range. The test chip was fabricated in TSMC 0.18 1P6M process, which core area is 0.11 um2. The power consumption at 6-GHz is 34.9mW with 1.8 V supply.

關鍵字(中)

★ 低電壓
★ 展頻時脈產生器
★ 多模數除頻器
★ 差異三角積分調變器

關鍵字(英)

★ sigma delta modulator
★ low voltage
★ Multi-modular divider
★ SSCG

論文目次

摘要 ii
誌謝 iv
Table of Contents v
List of Figures vii
List of Table x
Chapter 1 Introduction 1
1-1 Motivation and Background 1
1-2 Thesis Organization 2
Chapter 2 Related Technology of SSCG 3
2-1 Electromagnetic Interference 3
2-2 Spread Spectrum Clocking Technology 3
2-3 Forward Body Bias 5
2-4 Multi-Modular Divider 8
2-5 Sigma-Delta Modulator 12
2-6 Jitter Considerations of SSCG 14
Chapter 3 0.5 V Spread Spectrum Clock Generator 16
3-1 Asymmetry Forward Body Bias with Channel Width Scaling 16
3-2 Overview of 0.5 V SSCG 19
3-2-1 Phase Frequency Detector 20
3-2-2 Low Voltage Charge Pump 22
3-2-3 Low Pass Filter 23
3-2-4 Gain Reduced Circuit 26
3-2-5 Voltage Control Oscillator 27
3-2-6 Phase Switching MMD 28
3-2-7 Accurate Enhanced Sigma-Delta Modulator 35
3-2-8 Triangular Wave Generator 43
3-2-9 Digital Coarse Tune 44
3-3 Simulation Results 45
3-4 Layout and Measurement Considerations 51
3-5 Measurement Results 56
Chapter 4 A Fully Differential 6-GHz SATA SSCG 62
4-1 Overview of 6-GHz SATA SSCG 62
4-1-1 Differential Charge Pump with CMFB 63
4-1-2 Differential Low Pass Filter 65
4-1-3 Fully Differential VCO 66
4-1-4 Modified CML Divider 68
4-2 Simulation Results 71
4-3 Layout and Measurement Considerations 74
4-4 Measurement Results 77
Chapter 5 Conclusion and Future Work 80
Reference 81

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指導教授

鄭國興、黃弘一
(Kuo-Hsing Cheng、Hong-Yi Huang)

審核日期

2009-7-13

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