多位元鍺奈米晶粒非揮發性記憶體單胞元之製作與特性研究

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：17

、訪客IP：18.117.170.135

姓名

張穎弘(Yin Home Zhang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

多位元鍺奈米晶粒非揮發性記憶體單胞元之製作與特性研究
(Fabrication and Characterization of Multi-Bit Nonvolatile Memory Cell with Ge Nanocrystals)

相關論文

★ 金屬-半導體-金屬光偵測器的特性	★ 非晶質氮化矽氫基薄膜發光二極體與有機發光二極體的光電特性
★ 具非晶質n-i-p-n層之氧化多孔矽發光二極體的光電特性	★ 低漏電流與高崩潰電壓大面積矽偵測器製程之研究
★ 具自行對準凹陷電極1x4矽質金屬-半導體-金屬光偵測器陣列的特性	★ 非晶矽射極異質雙載子電晶體與有機發光二極體的特性
★ 吸光區累崩區分離的累崩光二極體	★ 蕭特基源/汲極接觸的反堆疊型非晶質矽化鍺薄膜電晶體
★ 矽晶圓上具有隔離氧化層非晶質薄膜發光二極體之光電特性	★ 具非晶異質接面及溝渠式電極之矽質金屬-半導體-金屬光偵測器的暗電流特性
★ 非晶矽/晶質矽異質接面矽基金屬-半導體-金屬光檢測器與具非晶質無機電子/電洞注入層高分子發光二極體之研究	★ 具非晶質矽合金類量子井極薄障層之高靈敏度平面矽基金屬–半導體–金屬光檢測器
★ 具蕭特基源/汲極的上閘極型非晶矽鍺與多晶矽薄膜電晶體	★ 大面積矽偵測器的製程改良與元件設計
★ 具組成梯度能隙非晶質矽合金電子注入層與電洞緩衝層的高分子發光二極體	★ 非晶質吸光區與累增區分離之類超晶格累崩光二極體

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

目前非揮發性記憶體在元件尺寸持續微縮的趨勢下，其需求為高密度記憶單元、低功率損耗、快速讀寫操作、以及良好的可靠度。奈米晶粒非揮發性記憶體可能取代傳統的浮動閘極記憶體，由於奈米晶粒可視為電荷存層中彼此分離的儲存點，可以有效改善小尺寸記憶體元件在多次操作後的資料儲存能力。
　　本論文的主題是研製以鍺奈米晶粒當作電荷儲存點的多位元密度非揮發性記憶體單胞元。首先探討製程步驟不太複雜的鍺奈米晶粒閘極堆疊層的性質，調整其製程參數使其可擁有最佳的電荷儲存效能，主要著重於大的記憶窗口、分佈均勻且密度高的鍺奈米晶粒層等特性。接著再將製程參數及效能最佳化的鍺奈米晶粒閘極堆疊應用多位元密度的非揮發性記憶體單胞元。單胞元係利用三維立體結構的設計，將電荷儲存點製作在矽洞的四側斜邊，使非揮發性記憶體單胞元擁有四個位元的儲存位置，此非揮發性記憶體單胞元製程與現階段的積體電路製程相容，所以具商業化的可能性。

摘要(英)

Current requirements of nonvolatile memory (NVM) for the scaling down device are high density cells, low-power consumption, high-speed operation and good reliability. The nonvolatile memories with nanocrystals are one of promising candidates to substitute for the conventional floating-gate memory, because the nanocrystals discrete charge storage nodes have effectively improved the data retention under endurance test for the scaling down device.
　　In this thesis, the multi-bit nonvolatile memory cell with Ge nanocrystals as the charge trapping nodes has been fabricated and demonstrated. Firstly, the Ge nanocrystals gate stack with rather simple fabrication process has been studied to optimize process conditions and performance (e.g. large memory window and high density Ge nanocrystals with uniform distribution, etc.). Then, the optimum Ge nanocrystals gate stack was used to fabricate the multi-bit NVM cell. The application of three-dimensional cell structure led the cell to the advantage of multi-bit capacity. The fabrication processes of this NVM cell were compatible with current IC manufacturing process. The multi-bit NVM cell studied commercialization in the feature.

關鍵字(中)

★ 三維結構
★ 鍺奈米晶粒
★ 多位元
★ TMAH蝕刻
★ 非揮發性記憶體

關鍵字(英)

★ TMAH etching
★ nonvolatile memory
★ multi-bit
★ 3-D structure
★ Ge nanocrystal

論文目次

Chapter 1　　　Induction...............................1
1-1 Overview of Nonvolatile memory.................1
Chapter 2 Operations of Nonvolatile Memory........5
2.1 Physics of Programming and Erase Mechanisms....5
2.1.1 Fowler-Nordheim Tunneling......................6
2.1.2 Channel Hot-Electron Injection.................8
2.2 Bandgap Structure of Multi-Bit NVM Cell.......10
2.3 Operation of Split-Gate Multi-Bit NVM Cell....13
Chapter 3 Fabrication and Characterization of Ge
Nanocrystals for NVMs.................15
3.1 Fabrication of Ge Nanocrystals................15
3.2 Characterization of Ge Nanocrystals...........19
3.2.1 AFM Topography of Ge Nanocrystals.............19
3.2.2 C-V Characteristics of Ge Nanocrystals........23
3.2.3 I-V Characteristics of Ge Nanocrystals........27
Chapter 4 Fabrication and Characterization of
Multi-Bit Nonvolatile Memory Cell
with Ge Nanocrystals..................30
4.1 Fabrication of Multi-Bit NVM Cell.............30
4.1.1 TMAH Etching Process TMAH for Silicon.........30
4.1.2 Fabrication of Multi-Bit NVM cell.............35
4.2 Characterization of Multi-Bit NVM Cells.......43
Chapter 5 Conclusion and Future Work............50
References............................................51

參考文獻

1.G. E. Moore, “Cramming More Components onto Integrated Circuits,” Proc. IEEE, Vol. 86, No. 1, pp. 82-85, Jan. 1998
2.International Technology Roadmap for Semiconductor, “ITRS Report 2008 Update,” 2008
3.F. Masuoka, “Semiconductor Memory Device and Method for Manufacturing the Sam,” U.S. Patent, No. 4531203, July 1985
4.J. De Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Trans. Nanotechnol., Vol. 1, No. 1, pp. 72-77, Mar. 2002
5.M. Inoue and J. Shirafuji, “(100) Si/SiO2 Interface States above Midgap Induced by Fowler-Nordheim Tunneling Electron Injection,” J. Appl. Phys., Vol. 80, No. 11, 6315, Dec. 1996
6.T. G. Ruskell, R. K. Workman, D. Chen, D. Sarid, S. Dhal, and S. Gillbert, “High Resolution Fowler-Nordheim Field Emission Maps of Thin Silicon Oxide Layers,” Appl. Phys. Lett., Vol. No. 1, 68, 93, Jan. 1996
7.B. Rössler, “Electrically Erasable and Reprogrammable Read-Only memory Using the n-Channel SIMOS One-Transistor Cell,” IEEE Trans. Electron Devices, Vol. 24, No. 5, pp. 606-610, May 1977
8.D. C. Guterman, I. H. Rimawi, T.-L. Chiu, R. D. Halvorson, and D. J. McElroy, “An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure,” IEEE Trans. Electron Devices, Vol. 26, No. 4, pp. 576-586, Apr. 1979
9.T. H. Ning, “Hot-Electron Emission from Silicon into Silicon Dioxide,” Solid-State Electron., Vol. 21, No. 1, pp. 273-282, Jan. 1978
10.N. Tsuji, N. Ajika, K. Yuzuriha, Y. Kunori, M. Hatanaka, and H. Miyoshi, “New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Endurance Characteristics,” IEEE IEDM Tech. Diag., pp. 53-56, Dec. 1994
11.M. Kamiya, Y. Kojima, Y. Kato, K. Tanaka, and Y. Hayashi, “EPROM Cell with High Gate Injection Efficiency,” IEEE IEDM Tech. Diag., pp. 741-744, Dec. 1982
12.J. Van Houdt, P. Heremans, L. Deferm, G. Groeseneken, and H. E. Maes, “Analysis of the Enhanced Hot-Electron Injection in Split-Gate Transistors Useful for EEPROM Applications,” IEEE Trans. Electron Devices, Vol. 39, No. 5, pp. 1150-1156, May 1992
13.M. Lenzlinger and E. H. Snow, “Fowler-Nordheim Tunneling into Thermally Grown SiO2,” J. Appl. Phys., Vol. 40, No. 1, pp. 278-283, Jan. 1969
14.E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Characterization of Channel Hot Electron Injection by the Subthreshold Slop of NROMTM Device,” IEEE Electron Device Lett., Vol. 22, No. 11, pp. 556, Nov. 2001
15.E. Lusky, Y. Shacham-Diamand, G. Mitengerg, A. Shappir, I. Bloom, and B. Eitan, “Investigation of Channel Hot Electron Injection by Localized Charge-Trapping Nonvolatile Memory Devices,” IEEE Trans. Electron Devices, Vol. 51, No. 3, pp. 444-451, Mar. 2004
16.C. Guérin, V. Huard, and A. Bravaix, “The Energy-Driven Hot-Carrier Degradation Modes of nMOSFETs,” IEEE Trans. Device Mater. Reliab., Vol. 7, No. 2, pp. 225-235, June 2007
17.C.-J. Sheu, “Electron Substrate and Gate current Modeling for Single-Drain Buried-Channel p-type Metal-Oxide-Semiconductor Field-Effect Transistors Including Tunneling Mechanisms,” Jpn. J. Appl. Phys., Vol. 47, No. 11, pp. 8248-8252, 2008
18.M.-T. Wu, H.-T. Lue, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineering SONOS (BE-SONOS),” IEEE Trans. Electron Devices, Vol. 54, No. 4, pp. 699-706, Apr. 2007
19.T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. sugahara, N. Ajika, and S.-I. Satoh, “Device Characteristics of 0.35 μm P-Channel DINOR Flash Memory Using Band-to-Band Tunneling-Induced Hot-Electron (BBHE) Programming,” IEEE Trans. Electron Devices, Vol. 46, No. 9, pp. 1866-1871, Sep. 1999
20.K. T. San, C. Kaya, and T. P. Ma, “Effect of erase Source Bias on flash EPROM Device Reliability,” IEEE Trans. Electron Devices, Vol. 42, No. 1, pp. 150-159, Jan. 1995
21.Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories – Part I: Device Design and Fabrication,” IEEE Trans. Electron Devices, Vol. 49, No. 9, pp. 1606-1613, Sep. 2007
22.G. Dai, H. Wolff, F. Pohlenz, and H.-U. Danzebrink, “A metrological Large Range Atomic Force Microscope with Improved Performance,” Rev. Sci. Instrum., Vol. 80, 043702, Apr. 2009
23.Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal Nanocrystal Memories – Part II: Electrical Characteristics,” IEEE Trans. Electron Devices, Vol. 49, No. 9, pp. 1614-1622, Sep. 2007
24.K. Biswas and S. Kal, “Etch Characteristics of KOH, TMAH and Dual Doped TMAH for Bulk Micromachining of Silicon,” Microelectron. J., Vol. 37, No. 6, pp. 519-525, June 2006
25.E. Steinsland, T. Finstad, and A. Hanneborg, “Etch Rates of (100), (111) and (100) Single-Crystal Silicon in TMAH Measured in Situ by Laser Reflectance Interferometry,” Sens. Actuator A-Phys., Vol. 86, No. 1-2, pp. 73-80, Oct. 2000

指導教授

洪志旺(Jyh-Wong Hong)

審核日期

2009-7-16

推文