寬範圍電壓操作之超低功率全數位式鎖相迴路

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姓名

陳俞佐(Yu-Tso Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

寬範圍電壓操作之超低功率全數位式鎖相迴路
(An Ultra Low Power All Digital PLL for WidePower Supply Range)

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摘要(中)

本論文提出一寬範圍電壓操作之超低功率全數位式鎖相迴路，不僅擁有低功率上的優點，並且在電源操作電壓上可從1.8 V 提升至3.6 V 的寬範圍設計，使用新型責任週期校正器電路獲得責任週期50%，並提出以環型振盪器和除頻器組合的數位控制振盪器之電路設計，使其可操作在寬範圍操作電壓。全數位式鎖相迴路晶片之製作以TSMC 0.35 um 2P4M 製程實現晶片，當操作電壓為1.8 V 時，其操作頻率範圍為1.5 MHz ~ 11.44 MHz，而操作電壓為3.6 V 時，其操作頻率範圍為1.5 MHz ~ 11.44 MHz，並且鎖定時間在23 個輸入週期內鎖定。整體晶片的面積為680 x 680 um2，核心電路的面積為383 x 368 um2 ，而新型責任週期校正器電路之責任週期在輸出頻率為8.38 MHz 時更可達50±0.8%，其輸出訊號之最大抖動量(P2P Jitter)的百分比為3% (操作電壓為1.8 V 為3.7 ns 而操作電壓為3.6 V 為3.6 ns)，並且可應用於數位電子式水表中之微處理器裡。在電流消耗部份操作電壓為1.8 V 時更只有36 uA，其功率消耗在操作電壓為1.8 V僅有64 uW 而在操作電壓為3.6 V 下也僅有234 uW。

摘要(英)

In this work, an ultra low power all digital phase locked loop(ADPLL) has wide power supply voltage range from 1.8 V to 3.6 V. ADPLL uses the proposed duty cycle corrector for 50% duty cycle. The ring oscillator and divider are used for digital controlled oscillator(DCO). Thus, DCO can operate wide power supply voltage range. ADPLL is implemented by TSMC 0.35 um 2P4M process. The output frequency range is 1.5 MHz ~ 11.44 MHz at 1.8 V, and output frequency range is 4.5 MHz ~ 24.49 MHz at 3.6 V. The locking time of ADPLL is less than 23 reference clock cycles. The chip area and core area are 680 x 680 um2 and 383 x 368 um2, respectively. The proposed duty cycle corrector is 50±0.8% at 8.38 MHz. The peak-to-peak jitter of ADPLL is 3% at 8.38 MHz for digital water meter application of microcontroller(3.7 ns at 1.8 V and 3.6 ns at 3.6 V). The operating supply current is less than 36 uA at 1.8 V, and power consumption is 64 uW at 1.8 V and 234 uW at 3.6 V.

關鍵字(中)

★ 全數位式鎖相迴路
★ 數位控制振盪器
★ 寬範圍電源電壓
★ 責任週期校正器
★ 低電源電流

關鍵字(英)

★ all digital PLL
★ digital controlled oscillator
★ duty cycle corrector
★ wide supply voltage range
★ low supply current.

論文目次

摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VII
表目錄 X
第一章緒論 1
1.1 研究動機 1
1.2 研究目的及用途 2
1.3 論文架構 4
第二章全數位式鎖相迴路先前技術探討 5
2.1 鎖相迴路種類簡介 5
2.1.1 線性鎖相迴路(LPLL) 5
2.1.2 數位式鎖相迴路(DPLL) 6
2.1.3 全數位式鎖相迴路(ADPLL) 7
2.2 全數位式鎖相迴路之設計考量 8
2.2.1. 低功率數位控制振盪器之全數位式鎖相迴路 [1] 8
2.2.2. 串接式動態頻率計數迴路之全數位式鎖相迴路 [2] 10
2.2.3. 寬範圍電壓操作之全數位式鎖相迴路 [3] 11
2.2.4. 可重組態數位濾波器之全數位鎖相迴路 [4] 12
2.2.5. 實現雜訊降低技術之全數位式鎖相迴路 [5] 14
2.3 全數位式鎖相迴路之設計期許 15
第三章具有新型責任週期校正器之數位控制振盪器 16
3.1 設計概念 16
3.2 數位控制振盪器 17
3.3 新型責任週期校正器 19
3.4 公式推導 23
第四章寬範圍電壓操作之超低功率全數位式鎖相迴路 26
4.1 電路架構與操作 26
4.1.1 鎖定流程圖 27
4.1.2 鎖定模式 28
4.2 控制器電路 30
4.3 逐漸近似暫存器電路 31
4.4 計數器電路 34
4.5 電流偵測器電路 35
4.6 比較器電路 40
4.7 準位轉換器電路 41
第五章電路模擬與晶片量測結果 43
5.1 設計流程 43
5.2 電路模擬 44
5.3 電路佈局與晶片照像圖 47
5.4 環境設定 50
5.5 量測結果 52
5.6 量測佈局比較 62
第六章結論與未來研究方向 64
6.1 結論 64
6.2 未來研究方向 65
參考文獻 66

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2009-10-19

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