應用於SATA-III之6 Gbps半速率時脈與資料回復電路

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姓名

陳炳宏(Bing-hung Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於SATA-III之6 Gbps半速率時脈與資料回復電路
(Design and Implementation of 6 Gbps Half-Rate Clock and Data Recovery Circuit for SATA-III Application)

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摘要(中)

由於近年來製程演進使得處理器及記憶體等運算單元及儲存元件之間的溝通量越來越大，傳統匯流排已不敷使用，因此高頻寬之收發器逐漸成為下一世代主流。高速傳輸技術的應用從光纖通訊發展到電腦通用I/O介面，經由電纜或匯流排作為傳輸媒介的高速串列介面。本論文之設計主要針對串列有線傳輸系統中的Serial-ATA III接收端規格為設計藍圖，採用雙迴路相位選擇式架構，利用半速率取樣方式實現時脈與資料回復電路。
本論文所設計實現的時脈與資料回復電路應用於6 Gbps的串列傳輸系統，輸出為二組3 Gbps並列資料。其中雙迴路相位選擇式架構分別由多相位時脈倍頻器與資料回復迴路所組成。其主要優勢在於二個獨立迴路，可以解決單一迴路中抖動轉移函數與抖動容忍度的頻寬互相衝突的問題。在資料回復迴路中，利用改良後的資料延遲視窗及取樣式相位偵測器取代傳統的半速率相位偵測單元，可降低對稱佈局走線難度和電路消耗功率；另外，資料追鎖頻寬以Serial-ATA III中的規格為基底，並加入頻寬可調機制，使迴路頻寬擁有較大的資料追鎖範圍。
在半速率取樣時脈與資料回復電路實現上，採用TSMC 0.13 μm 1P8M CMOS製程，供應電源為1.2 V，取樣速率為3 Gsps，經模擬驗證輸出回復時脈抖動為8.31 ps，並列輸出的回復資料抖動均小於16.3 ps。

摘要(英)

According to process evolution, the volume of the data transferring between processor and memory cells is larger and larger. This progress making the conventional data bus can not deal with such huge rate. Hence, wide bandwidth transmitter and receiver become the trend of the next generation. The SERDES technology adopts cable or data bus as high speed serial interface. It applies from fiber communication to general computer interface.
The clock and data recovery circuit designed in this thesis applies to 6 Gbps serial link system. The output of recovery data are two sets of 3 Gbps data stream in parallel. The dual loop phase selecting structure is composed of multi-phase phase lock loop and data recovery loop. The advantage of this architecture is that two loops are independent in each other. It can solve the conflict between jitter transfer function and jitter tolerance in single loop. In data recovery loop, it utilizes improved data delay window and sampling phase detector to replace conventional half-rate phase detector. It can simplify the difficulty in symmetrical layout and decrease the power consumption. Otherwise, the data tracking bandwidth is based on Serial-ATA III specification, and it equips with the function of tunable tracking bandwidth. Thus, the clock and data recovery circuit has larger data tracking range.
In implementation of half-rate clock and data recovery circuit, it utilizes TSMC 0.13 μm 1P8M CMOS process. The power supply is 1.2 V and sampling rate is 3 Gbps. The peak to peak jitter of recovery clock is 8.31 ps, and the recovery data jitter is less than 16.3 ps by simulation verification.

關鍵字(中)

★ 混和訊號
★ 鎖相迴路
★ 時脈與資料回復電路

關鍵字(英)

★ mixed-signal
★ phase lock loop
★ clock and data recovery

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x
表目錄 x
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章抖動分析 5
2.1 抖動簡介 5
2.1.1 隨機抖動 6
2.1.2 可預測性的抖動 7
2.1.3 眼圖分析 10
2.2 時脈與資料回復電路的抖動參數 11
2.2.1 抖動產生 11
2.2.2 抖動轉移函數 12
2.2.3 抖動峰值 13
2.2.4 抖動容忍度 14
第3章時脈與資料回復電路背景 17
3.1 時脈與資料回復電路簡介 17
3.1.1 串列連接與並列連接 17
3.1.2 資料形式 18
3.2 取樣速率 19
3.3 傳統時脈與資料回復電路架構 20
3.3.1 鎖相迴路式時脈與資料回復電路 20
3.3.2 延遲鎖相迴路式時脈與資料回復電路 22
3.3.3 超取樣式時脈與資料回復電路 23
3.3.4 突發式時脈與資料回復電路 24
3.3.5 相位選擇式時脈與資料回復電路 25
第4章時脈與資料回復電路實現 27
4.1 電路架構 27
4.2 多相位時脈倍頻電路 29
4.2.1 時脈倍頻電路線性模型 29
4.2.2 系統分析與模擬 31
4.2.3 相位頻率偵測器 33
4.2.4 電荷充電泵 35
4.2.5 壓控振盪器 37
4.2.6 迴路濾波器 40
4.2.7 除頻電路 42
4.3 資料回復電路 43
4.3.1 資料回復電路架構 44
4.3.2 抖動容忍度頻寬分析 45
4.3.3 相位偵測器 48
4.3.4 數位濾波器 55
4.3.5 相位旋轉器 58
4.3.6 相位調整器 60
4.3.7 輸入輸出驅動電路 63
第5章晶片模擬與量測 67
5.1 時脈倍頻器之模擬 67
5.2 資料回復電路之模擬 69
5.2.1 一倍頻寬系統鎖定之模擬 69
5.2.2 兩倍頻寬系統鎖定之模擬 70
5.2.3 五倍頻寬系統鎖定之模擬 72
5.2.4 規格比較表 74
5.3 晶片佈局圖 76
5.4 量測結果 78
5.4.1 量測環境 78
5.4.2 時脈倍頻器之量測結果 79
5.4.3 資料回復電路之量測結果 83
第6章結論 87
6.1 結論 87
6.2 電路未來改進方向 88
6.2.1 迴授時脈輸出驅動電路 88
6.2.2 電流模式預先除頻器 89
6.2.3 相位調整器電路 92
參考文獻 93

參考文獻

[1] PCI Express™ Base Specification , Gen2 Rev 0.3, Jul. 27, 2005.
[2] Serial ATA Workgroup “SATA: High speed Serialized AT Attachment,” Revision 2.6, Feb. 2006.
[3] Agilent Technologies “Jitter Fundamental & Measurement Technology,”.
[4] M. Aoyama, K. Ogasawara, and M. Sugawara “3Gbps, 5000ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for Serial ATA,” IEEE Symp. on VLSl Circuits Digest of Technical Papers 8-4, pp. 107-110, Jun. 2003.
[5] C. Emmerich “Introduction to Jitter,” Product Marketing Engineer, Wavecrest, Oct. 2001.
[6] Understanding Jitter, WAVECREST Corporation, 2001.
[7] Agilent Technologies “Measuring Jitter in Digital Systems ,” Application Note 1448-1.
[8] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE J. of Solid-State Circuits, vol. 36, no. 5, pp. 761-767, May 2001.
[9] B. Razavi, “Design of Integrated Circuit for Optical Communications,” McGraw-Hill Inc., International Edition, 2003.
[10] T. H. Lee and J. F. Bulzacchelli, “A 155-MHz clock recovery delay- and phase-locked loop,” IEEE J. of Solid-State Circuits, vol. 27, no. 12, pp. 1736-1746, Dec. 1992.
[11] X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS data recovery DLL using half-frequency clock,” IEEE J. of Solid-State Circuits, vol. 37, no. 6, pp. 711-715, Jun. 2002.
[12] J. Kim and D.-K. Jeong, “Multi-gigabit-rate clock and data recovery based on blind oversapmling,” IEEE Communications Magazine, vol. 41, pp. 68-74, Dec. 2003.
[13] M. Banu and A. Dunlop, “A 660Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1993, pp. 102-103.
[14] P. Larsson, “A 2-1600 MHz CMOS clock recovery PLL with low-Vdd capability,” IEEE J. of Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Dec. 1999.
[15] M. Nogawa, K. Nishimura, S. Kimura, and T. Yoshida, et al. “A 10-Gb/s burst-mode CDR IC in 0.13μm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., vol. 1, Feb. 2005, pp. 228-229.
[16] R. E. Best, “Phase-Locked Loops: Design, Simulation and Applications,” New York: McGraw-Hill, Fourth Ed., 1999.
[17] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. of Solid-State Circuit, vol. 31, no. 3, pp. 331-343, Mar. 1996.
[18] C.–H. Park et al.,”A low-noise, 900MHz VCO in 0.6μm CMOS,” IEEE J. of Solid-State Circuits, vol. 34, no. 5, pp. 586-591, May 1999.
[19] S.–J. Lee et al., ”A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE J. of Solid-State Circuits, vol. 32, no. 2, pp. 289-291, Feb.1997.
[20] M. M. Green and U. Singh, “Design of CMOS CML circuits for high-speed broadband communications,” in Proc. IEEE Int. Symp. Circuits and System, vol. 2, May 2003, pp. 204-207.
[21] Y. Miki, T. Saito, and H. Yamashita, et al. “A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking,” IEEE J. of Solid-State Circuits, vol. 39, no. 4, pp. 613-621, Apr. 2004.
[22] J. Lee, K. S. Kundert, and B. Razavi, “Analisis and modeling of bang-bang clock and data recovery circuits,“ IEEE J. of Solid-State Circuits, vol. 39, pp. 1571-1580, Sep. 2004.
[23] G. M. Yin, F. O. Eynde, and W. Sansen, “A high-speed CMOS comparator with 8-b resolution,” IEEE J. of Solid-State Circuits, vol. 27, no. 2, pp. 208-211, Feb. 1992.
[24] S. Sidiropoulos and M. A. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. of Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
[25] M. M. Green, “CMOS design techniques for 10 Gb/s optical transceivers,” IEEE Symp. on VLSl Circuits, pp. 209-212, May 2003.
[26] R. Kreienkamp, U. Langmann, and C. Zimmermann, et al. “A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, pp. 736-743, Mar. 2005.
[27] M. Y. He and J. Poulton, “A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver,” IEEE J. of Solid-State Circuits, vol. 41, no. 3, pp. 597-606, Mar. 2006.
[28] P. K. Hanumol, G. Y. Wei, and U. K. Moon, “A wide-tracking range clock and data recovery circuit,” IEEE J. of Solid-State Circuits, vol. 43, no. 2, pp. 425-439, Feb. 2008.
[29] Y.-S. Seo, J.-W. Lee, H.-J.g Kim, C. Yoo, J.-J. Lee, and C.-S. Jeong, “A 5-Gbit/s clock and data recovery circuit with 1/8-rate linear phase detector in 0.18μm CMOS technology,” IEEE Trans. on Circuits and Systems II, vol. 56, pp. 6-10, Jan. 2009
[30] Y. Amamiya, S. Kaeriyama, H. Noguchi, Z. Yamazaki, T. Yamase, K. Hosoya, M. Okamoto, S. Tomari, H. Yamaguchi, H. Shoda, H. Ikeda, S. Tanaka, T. Takahashi, R. Ohhira, A. Noda, K. Hijioka, A. Tanabe, S. Fujita, and N. Kawahara, “A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 358-359, 359a.
[31] Anritsu “Ultra-Wideband Bias Tees Models K251 and V251,” Revision A, Jun. 2000.

指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2009-10-19

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