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姓名	傅挺峻(Ting-Jun Fu)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	應用於隨機存取記憶體診斷之內建診斷的資料壓縮技術 (Built-In Diagnostic Data Compression Techniques for Random Access Memories)
相關論文	★ 應用於三元內容定址記憶體之低功率設計與測試技術 ★ 用於隨機存取記憶體的接線驗證演算法 ★ 用於降低系統晶片內測試資料之基礎矽智產 ★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法 ★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試 ★ 用於系統晶片中單埠與多埠記憶體之自我修復技術 ★ 用於修復嵌入式記憶體之基礎矽智產 ★ 自我修復記憶體之備份分析評估與驗證平台 ★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計 ★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計 ★ 低功率與可自我修復之三元內容定址記憶體設計 ★ 多核心系統晶片之診斷方法 ★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產 ★ 應用於貪睡靜態記憶體之有效診斷與修復技術 ★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案 ★ 應用於隨機存取記憶體之有效良率及可靠度提升技術
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摘要(中)	隨著電晶體尺寸的縮減和侵略性的設計規則 (aggressive design rule)，記憶體患有嚴重的良率和可靠度問題。因此在現今的記憶體中，有效的可靠度和良率提升技巧是必要的。記憶體診斷被廣泛應用於強化記憶體設計或是製造過程，進而提升良率和可靠度。自我診斷 (built-in self-diagnosis，BISD) 方法已經被廣泛應用於嵌入式記憶體的診斷。 典型的自我診斷電路透過單一輸出腳位序列輸出診斷的資料。然而，在一個系統晶片 (system-on-chip，SOC) 中，一般有很多記憶體，因此診斷的資料量可能非常龐大。資料壓縮技巧可應用於減少診斷資料的輸出時間。在論文中我們提出三個診斷資料壓縮的技巧。論文第一個部份提出應用於多個同質性記憶體的階層式 (multi-level) 壓縮方法，此方法可以有效地減少診斷的資料，而且實現的壓縮電路面積成本非常低。從實驗結果可得知，假設一個256-位元的漢明症狀 (Hamming syndrome，HS) 被切割成8-位元符號，對於三個同質性記憶體，平均壓縮率 (compression ratio，CR) 大約是11%。若使用台積電0.18-微米 (TSMC 0.18-μm) 製程實現自我診斷電路包括階層式的壓縮器，用於三個8Kx16同質性記憶體，則自我診斷電路所需的邏輯閘個數是2126，也就是自我診斷電路的面積負擔為0.84%。 論文第二個部份提出以行軍式元素為基礎 (March-element-based，MEB) 診斷資料壓縮的方法。當執行一個應用於偵測靜態和動態故障的行軍式測試演算法，所產生的記憶體診斷資料可有效地被此方法壓縮。從實驗結果得知，對於一個512x256-位元記憶體執行行軍式-DD (March-DD) 演算法，平均壓縮率大約是36.08%。若使用台積電0.18-微米製程實現自我診斷電路包括行軍式元素為基礎的壓縮器，用於一個8Kx64-位元記憶體，則自我診斷電路所需的邏輯閘個數是5881，也就是自我診斷電路的面積負擔為2.03%。 論文最後一個部份提出以錯誤位元編碼的方法做診斷資料壓縮，對於不同的瑕疵的樣本，此方法可以大大地改善壓縮率。以一個512x256-位元記憶體為例，平均的壓縮率大約是8.09%。若使用台積電0.18-微米製程實現自我診斷電路包括錯誤位元編碼的壓縮器，用於一個8Kx64-位元記憶體，則自我診斷電路所需的邏輯閘個數是6761，也就是自我診斷電路的面積負擔為2.17%。
摘要(英)	Yield and reliability are two very critical challenges for modern random access memories (RAMs). With the shrinking transistor size and aggressive design rules, RAMs are easily prone to severe yield and reliability problems. Therefore, efficient reliability-enhancement and yield-enhancement techniques are imperative for modern RAMs. Memory diagnosis is a widely used technique for the enhancement of memory design or manufacture process such that the yield and reliability of the memory design are increased. Built-in self-diagnosis (BISD) technique has been widely used for the diagnosis of embedded RAMs. A BISD design typically exports diagnostic data serially through a single output. For a system-on-chip (SOC), many RAM cores exist. Thus, the amount of diagnostic data may be very huge. To reduce the exportation time of diagnostic data, data compression technique can be applied. In this thesis, three diagnostic data compression techniques are proposed. First, a multi-level compression scheme for multiple homogeneous RAMs is proposed. The multilevel compression scheme for multiple homogeneous RAMs can efficiently reduce diagnostic data and the area cost for realizing the compression circuit is very small. Experimental results show that if a 256-bit Hamming syndrome is partitioned into 8-bit symbols, the average compression ratio (the ratio of the number bits of the compressed data to that of the original data) is about 11% for three 128k-bit homogeneous memories. A BISD with the multi-level compressor has been realized using TSMC 0.18-um technology. The total gate count of the proposed BISD circuit for three 8K×16 homogeneous memories is 2126, i.e., the area overhead of the BISD circuit is about 0.84%. In addition, a March-element-based (MEB) diagnostic data compression scheme for RAMs with static and dynamic faults is proposed. The MEB diagnostic data compression scheme can efficiently compress diagnostic data of a RAM tested by a March test for detecting static and dynamic faults. Experimental results show that the average compression ratio is about 36.08% for a 512×256-bit memory tested with 100% single cell fault by March-DD algorithm. A BISD with the MEB compressor has also been designed using TSMC 0.18-um technology. The area overhead of the BISD is about 2.03% for an 8K×64-bit RAM. Finally, a diagnostic data compression using faulty-bit encoding (FBE) scheme for RAMs is proposed. The FBE scheme can greatly improve compression ratio for a RAM with different fail patterns. Experimental results show that the FBE scheme has good CR for a RAM with different fail patterns. The average CR is about 8.09% for a 512×256-bit RAM. A BISD with FBE compressor has been implemented using TSMC 0.18-um technology. The gate count of the proposed BISD for an 8K×64-bit memory is 6761, i.e., the area overhead of the BISD circuit is about 2.17%.
關鍵字(中)	★ 診斷資料壓縮 ★ 自我診斷 ★ 隨機存取記憶體	關鍵字(英)	★ Diagnostic Data Compression ★ Random Access Memory ★ Built-In Self-Diagnosis
論文目次	1 Introduction 1 1.1 BISD Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Tree-Based Compression Method . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.1 Huffman Tree Coding Technique . . . . . . . . . . . . . . . . . . . . . 3 1.3 Distinguish Fail Patterns Method . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Using Differential Address Technique . . . . . . . . . . . . . . . . . . . . . . 6 2 A Multi-Level Compression Scheme for Multiple Homogeneous RAMs 9 2.1 Multi-Level Compression Method . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Design of Diagnostic Data Compression Module . . . . . . . . . . . . . . . . 13 2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 Compression Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 Results of Hardware Implementation . . . . . . . . . . . . . . . . . . 25 3 March-Element-Based Diagnostic Data Compression Scheme for RAMs with Static and Dynamic Faults 28 3.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 Testing and Diagnosis of Static and Dynamic Faults . . . . . . . . . . . . . . 30 3.3 March-Element-Based Diagnostic Data Compression Scheme . . . . . . . . . 31 3.4 Design of A BISD with MEB Compressor . . . . . . . . . . . . . . . . . . . . 34 3.5 Decompression Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.6 Reconfigurable BISD Scheme for Multiple RAMs . . . . . . . . . . . . . . . 40 3.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 Diagnostic Data Compression Using Faulty-Bit Encoding Scheme 47 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3 Faulty-Bit Encoding Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 Architecture of A BISD with FBE Compressor . . . . . . . . . . . . . . . . . 50 4.5 Reconfigurable BISD Scheme for Multiple RAMs . . . . . . . . . . . . . . . 55 4.6 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.1 Compression Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6.2 Results of Hardware Implementation . . . . . . . . . . . . . . . . . . 58 5 Conclusions and Future Works 64 5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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指導教授	李進福(Jin-Fu Li)	審核日期	2009-11-19
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