適用IEEE 802.16e標準之多碼率單埠記憶體LDPC解碼器設計

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姓名

張緯淞(Wei-Sung Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用IEEE 802.16e標準之多碼率單埠記憶體LDPC解碼器設計
(Design of Multi-Code Rate LDPC Decoder with Single Port Memory for IEEE 802.16e Standard)

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摘要(中)

本篇論文提出可適用於IEEE 802.16e標準的多碼率LDPC解碼器，目前LDPC解碼器在序列化的架構上，記憶體的使用率是很高的，在減少面積與硬體複雜度的前提下，記憶體所佔有的比重也會越來越大。同時為了使速度達到最佳化，用管線技術增加硬體使用率，記憶體必須具備同時讀寫的能力，因此採用雙埠記憶體的LDPC解碼器是普遍的。本篇論文特別針對此記憶體做優化與改良，採用單埠記憶體來取代雙埠記憶體，單埠記憶體比起雙埠記憶體在功率與面積上都佔有優勢，如何在相同記憶容量與不增加速度的前提下，將雙埠記憶體取代是本論文的重點。單埠的缺點在於不能同時間讀寫，因此在資料存取的排序上必須特別規劃，本論文針對IEEE 802.16e標準其六種檢查矩陣特別設計對應的資料排程以及資料在記憶體的位置，同時將記憶區塊拉出檢查節點與位元節點形成共用的第三區塊。經由FPGA驗證得知，單埠記憶體可完全取代雙埠記憶體以節省面積與功率，但在速度上會隨著檢查矩陣碼率的提高，而略劣於雙埠記憶體。由ISE軟體合成電路後可知本論文LDPC所提出之架構可以有最高112.94Mbps的生產量。

摘要(英)

This thesis proposes a multi-code rate LDPC decoder in the application of IEEE 802.16e. The utilization rate of memory is very high when the LDPC decoder uses a serial architecture. To reduce the complexity of hardware, the percentage of memory unit is getting higher. In order to optimize the throughput rate, pipline technique can increase the hardware utilization. However, such architecture needs the memory to read and write at the same time. Hence the LDPC decoder usually uses two-port memory. This thesis focuses on the optimization and modification of memory design. We use single-port memory to replace two-port memory because single-port memory has the advantage of power consumption and area. The weakness of single-port memory is it cannot read and write at the same time. We should carefully arrange the data access schedule. In this thesis, we have designed the memory access schedules according to six parity check matrices for IEEE 802.16e. In the FPGA emulation results, single-port memory can completely replace the two port memory to save the chip area and power consumption. The throughput rate would be lower than two-port memory architecture as the code rate increases. Finally, the throughput rate of the proposed LDPC decoder can achieve 112.94 Mbps.

關鍵字(中)

★ 多碼率LDPC 解碼器設計
★ 單埠記憶體模式解碼器

關鍵字(英)

★ Multi-Code Rate LDPC Decoder
★ Single Port Memory for IEEE 802.16e Standard

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 viii
第一章緒論 1
1.1 背景與研究動機 1
1.2 論文架構 2
第二章低密度同位元檢查碼 3
2.1 線性區塊碼 3
2.2 低密度同位元檢查碼簡介 4
2.3 低密度同位元檢查碼在IEEE 802.16e 的標準資訊 6
第三章低密度同位元檢查碼的編碼方法與解碼方法 7
3.1 LDPC編碼原理 7
3.2 LDPC常用解碼演算法簡介 8
3.2.1 SPA 9
3.2.2 LLR 11
3.2.3 MSA 13
3.2.4 Modified MSA 14
3.2.5 Offset MSA 15
3.3 LLR演算法在IEEE 802.16e各碼率下的效能表現 16
第四章 IEEE 802.16e各碼率記憶體排序 17
4.1 解碼矩陣重新排列與記憶體資料排序方法 17
4.2 各碼率資料執行順序與記憶體位置 17
4.2.1 IEEE 802.16e解碼矩陣碼率：1 / 2 18
4.2.2 IEEE 802.16e解碼矩陣碼率：2 / 3 A 21
4.2.3 IEEE 802.16e解碼矩陣碼率：2 / 3 B 23
4.3.4 IEEE 802.16e解碼矩陣碼率：3 / 4 A 24
4.3.5 IEEE 802.16e解碼矩陣碼率：3 / 4 B 26
4.3.6 IEEE 802.16e解碼矩陣碼率：5 / 6 27
4.3 單埠記憶體與雙埠記憶體在六種矩陣的速度差異 29
第五章硬體實現 30
5.1 平行架構 30
5.2 序列架構 31
5.3 IEEE 802.16e設計架構 31
5.3.1 整體架構 33
5.3.2 檢查節點架構 34
5.3.3 位元節點架構 35
5.3.4 記憶區塊架構 36
5.3.5 線路轉換架構 37
5.4 量化 38
5.4.1 LUT 38
5.4.2 檢查節點端 40
5.4.3 位元節點端 44
5.5 FPGA驗證 48
第六章結論 52
6.1 結論 52
6.2 未來展望 52
參考文獻 53

參考文獻

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2009-12-7

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