應用於動態隨機存取記憶體之自我測試輔助復新功率降低技術

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張家銘(Chia-Ming Chang) 查詢紙本館藏

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電機工程學系

論文名稱

應用於動態隨機存取記憶體之自我測試輔助復新功率降低技術
(BIST-Assisted Refresh Power Reduction Techniques for DRAMs)

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摘要(中)

動態隨機存取記憶體（dynamic random access memory, DRAM）為電子系統中關鍵的元件之一。一個DRAM單元(cell)是由一個電晶體和一個電容所構成。其中，電晶體被用於存取電容，藉由在電容中的電荷量來表示儲存在DRAM單元中的資料。由於漏電電流的關係，DRAM需要週期性地復新(refresh)以確保儲存資料的正確性。然而，復新操作是一個需要消耗功率的動作，在DRAM功率消耗上占了很大的部分。因此，發展有效的復新功率降低技術對於設計低功耗的DRAM是非常重要的。

多樣復新週期(multiple-refresh-period, MRP)的方法是有效的復新功率降低技術之一。使用多樣復新週期方法，DRAM可以使用不同的復新週期去刷新DRAM的區塊(block)。然而，如何識別每個DRAM區塊各自的復新週期是一個問題。因此在本論文的第一部分，提出一個復新週期分類測試(refresh period classifying test, RPCT)方法來識別DRAM區塊的復新週期。並且，提出一個內建自我測試(built-in self-test, BIST)設計用來支援所提出的復新週期分類測試方法。由分析結果觀察可知，與既有的方法相比，所提出的測試方法可以使用較短的測試時間去識別DRAM區塊的復新週期。因此，所提出的測試方法與既有的方法相比可以降低35.2％到30.9％的測試時間。

為了提升多樣復新週期方法的有效性，在本論文的第二部分提出一個位址重映射(address remapping)的方法用以減少在一個DRAM區塊中DRAM列(row)的復新週期的多樣性。換句話說，所提出的位址重映射方法可以增加在DRAM中DRAM區塊的復新週期的多樣性，使得在使用多樣復新週期方法時可以降低更多的復新功率消耗。並且，提出一個位址交換演算法(address swapping algorithm)來產生位址重映射表(address remapping table)。最後，提出一個內建自我測試電路來實現所提出的位址重映射方法。由分析結果觀察可知，對於DRAM有256個區塊和16個可定址內容記憶體(CAM)條目的情況下，所提出的位址重映射方法可以節省26.62％的功率消耗。

摘要(英)

Dynamic random access memory (DRAM) is one key component in electronic systems. A DRAM cell is composed of one transistor and one capacitor. The transistor is used to access the capacitor in which the amount of charge represents the data stored in the DRAM cell. Due to the leakage current, the DRAM needs to be refreshed periodically to ensure the data integrity. However, the refresh operation is a power-consumption operation, which represents a significant portion of the DRAM power consumption. Developing effective refresh power reduction techniques thus is imperative for designing a low-power DRAM.

Multiple-refresh-period (MRP) method is one of effective refresh power reduction techniques. A DRAM with MRP method can refresh DRAM blocks using different refresh periods. However, how to identify individual refresh period of each DRAM block is an issue. In the first part of this thesis, a refresh period classifying test (RPCT) method is proposed to identify the refresh periods of DRAM blocks in a DRAM. Also, a built-in self-test (BIST) design supporting the RPCT method is proposed. Analysis results show that the proposed method can identify the refresh periods of DRAM blocks using shorter test time in comparison with existing works. The proposed test method can achieve 35.2 % to 30.9 % test time reduction in comparison with existing works.

To enhance the effectiveness of MRP method, furthermore, an address remapping approach is proposed to minimize the diversity of refresh periods of rows in a DRAM block in the second part of this thesis. The proposed address remapping approach can enlarge the diversity of refresh periods of DRAM blocks such that more refresh power reduction can be achieved by using MRP method. An address swapping algorithm is proposed to generate the address remapping table as well. Finally, a BIST design with the address remapping method is realized. Analysis results show that the proposed address remapping approach can achieve 26.62 % power saving for a DRAM with 256 blocks and 16 CAM entries.

關鍵字(中)

★ 動態隨機存取記憶體
★ 內建自我測試
★ 復新

關鍵字(英)

★ DRAM
★ BIST
★ refresh

論文目次

Contents
1 Introduction 1
1.1 DRAM Architecture and Operations . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Testing Issues of DRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Targeted Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 DRAM Test Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Low-Power Refresh Techniques for DRAMs . . . . . . . . . . . . . . . . . . . 9
2 A Test Method for Classifying Refresh Periods of DRAMs 13
2.1 Block-Based Multiple-Refresh-Period Refresh Technique . . . . . . . . . . . . 13
2.2 Classifying Refresh Periods of the DRAM . . . . . . . . . . . . . . . . . . . . 16
2.3 Proposed Refresh Period Classifying Test Methodology . . . . . . . . . . . . 17
2.3.1 Proposed Test Flow for DRAMs . . . . . . . . . . . . . . . . . . . . . 17
2.3.2 Refresh Period Classifying Test Algorithm . . . . . . . . . . . . . . . 18
2.4 BIST with Refresh Period Classifying Test Function . . . . . . . . . . . . . . 21
2.4.1 Proposed Built-In Self-Test Architecture . . . . . . . . . . . . . . . . 21
2.4.2 Design of BIST CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.3 Design of TPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.4 Design of CLASS CTR . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.5 Data Retention Test Issues . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5 Analysis and Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Refresh Power Reduction Technique for DRAMs Using Address Remapping Method 34
3.1 Proposed Refresh Power Reduction Technique . . . . . . . . . . . . . . . . . 34
3.1.1 Concept of Refresh Power Reduction Using Address Remapping . . . 34
3.1.2 Proposed Address Remapping Scheme . . . . . . . . . . . . . . . . . 36
3.1.3 Proposed Address Swapping Algorithm . . . . . . . . . . . . . . . . . 39
3.1.4 Proposed Test Flow for DRAMs . . . . . . . . . . . . . . . . . . . . . 42
3.2 BIST with Proposed Refresh Power Reduction Technique . . . . . . . . . . . 44
3.2.1 BIST Modification for Proposed Refresh Power Reduction Technique 44
3.2.2 Design of Modified TPG . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.3 Design of Modified CLASS CTR . . . . . . . . . . . . . . . . . . . . 46
3.2.4 Design of Proposed ASA CTR . . . . . . . . . . . . . . . . . . . . . . 47
3.3 Analysis and Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Conclusion and Future Work 57
Bibliography 59

參考文獻

[1] Micron, “DDR3 SDRAM,” http://www.micron.com/˜/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb DDR3 SDRAM.pdf.
[2] J. Kim and M. C. Papaefthymiou, “Block-based multiperiod dynamic memory design for low data-retention power,” IEEE Trans. on VLSI Systems, vol. 11, no. 6, pp. 1006–1018, Dec. 2003.
[3] V. Nathan and N. C. Das, “Gate-induced drain leakage current in MOS devices,” IEEE Trans. on Electron Devices, vol. 40, no. 10, pp. 1888–1890, Oct. 1993.
[4] T. Hamamoto, S. Sugiura, and S. Sawada, “On the retention time distribution of dynamic random access memory (DRAM),” IEEE Trans. on Electron Devices, vol. 45, no. 6, pp. 1300–1309, June 1998.
[5] P. G. Emma, W. R. Reohr, and M. Meterelliyoz, “Rethinking refresh: increasing availability and reducing power in DRAM for cache applications,” IEEE Micro, vol. 28, no. 6, pp. 47–56, Nov. 2008.
[6] R.-F. Huang, H.-Y. Yang, M. C. Chao, and S.-C. Lin, “Alternate hammering test for application-specific DRAMs and an industrial case study,” in Proc. IEEE/ACM Design Automation Conf. (DAC), June 2012, pp. 1012–1017.
[7] Y. Idei, K. Shimohigashi, M. Aoki, H. Noda., H. Iwai, K. Sato, and T. Tachibana, “Dualperiod self-refresh scheme for low-power DRAM’s with on-chip PROM mode register,” IEEE Jour. of Solid-State Circuits, vol. 33, no. 2, pp. 253–259, Feb. 1998.
[8] R. K. Venkatesan, S. Herr, and E. Rotenberg, “Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM,” in Int’l Symp. on High-Performance Computer Architecture, Feb. 2006, pp. 155–165.
[9] J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, “RAIDR: retention-aware intelligent DRAM refresh,” in Proc. on Int’l Symp. on Computer Architecture, June 2012, pp. 1–12.
[10] J.-H. Ahn, B.-H. Jeong, S.-H. Kim, S.-H. Chu, S.-W. Cho, H.-J. Lee, M.-H. Kim, S.-I. Park, S.-W. Shin, J.-H. Lee, B.-S. Han, J.-K. Hong, P. B. Moran, and Y.-T. Kim, “Adaptive self refresh scheme for battery operated high-density mobile DRAM applications,” in IEEE Asian Solid-State Circuits Conf., Nov. 2006, pp. 319–322.
[11] S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn, “Flikker: saving DRAM refresh-power through critical data partitioning,” in Proc. of Int’l Conf. on Architectural Support for Programming Languages and Operating Systems, Mar. 2011, pp. 213–224.
[12] T. Nagai, M. Wada, H. Iwai, M. Kaku, A. Suzuki, T. Takai, N. Itoga, T. Miyazaki, H. Takenaka, T. Hojo, and S. Miyano, “A 65nm low-power embedded DRAM with extended data-retention sleep mode,” in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), Feb. 2006, pp. 567–576.
[13] Y. Katayama, E. J. Stuckey, S. Morioka, and Z. Wu, “Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention,” in Int’l Symp. on Defect and Fault Tolerance in VLSI Systems, Nov. 1999, pp. 311–318.
[14] S.-S. Pyo, C.-H. Lee, G.-H. Kim, K.-M. Choi, Y.-H. Jun, and B.-S. Kong, “45nm lowpower embedded pseudo-SRAM with ECC-based auto-adjusted self-refresh scheme,” in Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), May 2009, pp. 2517–2520.
[15] J. Kim and M. C. Papaefthymiou, “Dynamic memory design for low data-retention power,” in Proc. PATMOS 10th Int’l Workshop Power and Timing Modeling, Optimization, and Simulation, Sept. 2000, pp. 207–216.
[16] S. Takase and N. Kushiyama, “A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme,” IEEE Jour. of Solid-State Circuits, vol. 34, no. 11, pp. 1600–1606, Nov. 1999.
[17] Y.-C. Yu, C.-S. Hou, L.-J. Chang, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A hybrid ECC and redundancy technique for reducing refresh power of DRAMs,” in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2013, pp. 208–213.
[18] I. Bhati, Z. Chishti, and B. Jacob, “Coordinated refresh: energy efficient techniques for DRAM refresh scheduling,” in Int’l Symp. on Low-Power Electronics and Design, Sept. 2013, pp. 205–210.
[19] G. Thomas, K. Chandrasekar, B. Akesson, B. Juurlink, and K. Goossens, “A predictorbased power-saving policy for DRAM memories,” in Euromicro Conf. on Digital System Design, Sept. 2012, pp. 882–889.
[20] M. G. adn H.-H. S. Lee, “Smart refresh: an enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs,” in IEEE/ACM International Symp. on Microarchitecture, Dec. 2007, pp. 134–145.
[21] R. Dekker, F. Beenker, and L. Thijssen, “A realistic fault model and test algorithm for static random access memories,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 6, pp. 567–572, June 1990.

指導教授

李進福(Jin-Fu Li)

審核日期

2014-8-26

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