考量製程變異與佈局效應的低壓降線性穩壓器自動化合成工具

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姓名

張馨如(Hsing-Ju Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

考量製程變異與佈局效應的低壓降線性穩壓器自動化合成工具
(Automatic Synthesis Tool for Low Dropout Regulator Considering Process Variations and Layout Effects)

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摘要(中)

隨著可攜式電子產品市場的盛行，為延長電池的工作時間，低功率成為可攜式電子產品的首要考量，而電源管理IC的需求也日漸增加。此外，由於日益激烈的市場競爭及緊縮的產品上市時間，高良率成為產業所追求的目標之一，因此一套可有效提升良率且縮短設計時間的自動化合成工具是必不可少的。

本論文提出一套考量製程變異與佈局效應的低壓降線性穩壓器自動化合成工具，可經由人性化的圖形介面，設計出符合需求規格的電路設計與電路佈局。為了提高良率評估的精準度，本論文以最壞情況距離(worst case distance)的概念來協助訂定良率的目標，並與布局效應一起整合到以方程式為基礎的自動化設計流程中，在自動化流程中並同時考慮誤差放大器(Error amplifier)和低壓降線性穩壓器的交互效應，以達成整體電路的最佳化，降低設計的成本。

本論文中的自動化合成工具已在Linux上實現，在線性規劃(linear programming)的部分使用CPLEX來找尋最佳解，而在自動產生電路佈局上則是以C/C++及Tcl/Tk 程式語言產生批次命令，再由Laker自動完成佈局的過程。從實驗數據的觀察可知，本論文所提出的工具可快速設計出符合使用者所給定規格之電路，在佈局後電路效能皆可達到所需求的規格，並可有效提升電路良率，達成高品質的需求。

摘要(英)

With the increasing demand of portable electronic devices, reducing power consumption has become the major concern to increase the battery life. The demand of power management ICs are also increasing in those electronic products. Moreover, due to the fierce market competition and the need of fast time-to-market, high design yield is also one of the major objectives in industry. Therefore, an automated synthesis tool is essential to shorten the design cycles and improve the design yield.

This thesis presents an automatic synthesis tool for low dropout regulator (LDO) considering process variations and layout effects. This tool can generate the required designs from specifications to layout through a user-friendly GUI. In order to optimize the design yield with accurate variation consideration, the worst case distance (WCD) concept is integrated into the layout-aware equation-based sizing approach in this work. The device in the low dropout linear regulator and its error amplifier are both considered in the optimization process for reducing the overall circuit cost.

The proposed sizing algorithm has been implemented in Linux with the LP solver CPLEX, incorporating with an automatic layout generation tool implemented with C/C++ and Tcl/Tk on Laker. As demonstrated in the experimental results, this synthesis tool is able to achieve the required specifications in a short time and significantly improve the design yield while the post-layout performance is still guaranteed.

關鍵字(中)

★ 低壓降線性穩壓器
★ 自動化合成工具
★ 製程變異
★ 佈局效應

關鍵字(英)

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第一章、緒論 1
1.1. 研究動機 1
1.2. 電壓轉換器的種類 5
1.3. 相關研究 8
1.4. 論文架構 13
第二章、背景 14
1. 14
2. 14
2.1. 低壓降線性穩壓器 14
2.1.1. 電路架構 14
2.1.2. 傳輸元件 15
2.1.3. 壓降電壓 17
2.1.4. 線性調節率 18
2.1.5. 負載調節率 19
2.1.6. 靜態電流 20
2.1.7. 轉換效率 21
2.2. 電壓驅動設計方法 22
2.2.1. 效能限制條件 23
2.2.2. gm/ID的特性 24
2.2.3. 設計尺寸 26
2.3. 良率分析 27
2.4. 佈局產生的寄生效應之影響 30
2.4.1. 電晶體內部寄生效應 31
2.4.2. 導線上寄生效應 32
2.5. 佈局環境介紹 33
2.5.1. Laker 與 Tcl / Tk 33
2.5.2. 電晶體 34
2.5.3. 電阻與電容 37
2.5.4. 防護環(guard ring) 40
第三章、自動化設計流程 42
3.1 考量製程變異與佈局效應自動化合成流程 42
3.2 低壓降線性穩壓器電路分析 43
3.2.1 穩態分析 44
3.2.2 穩定度條件 45
3.2.3 穩定時間 50
3.2.4 靜態功率消耗 51
3.2.5 效能 53
3.3 階層式變異度考量方法 56
3.4 考慮寄生效應之自動化電路設計步驟 60
3.4.1 電晶體內部的寄生效應 61
3.4.2 導線上的寄生效應 63
第四章、自動化設計工具 65
4.1 簡介 65
4.2 工具介面操作 66
第五章、實驗結果與分析 72
5.1 實驗環境 72
5.2 實驗結果 72
5.2.1 兩級式運算放大器N型 73
5.2.2 兩級式運算放大器P型 76
5.2.3 電流鏡運算放大器 79
5.2.4 其他實驗結果比較 82
第六章、結論 84
參考文獻 85

參考文獻

[1] “IHS iSuppli Research” , Dec. 2012
[2] J.-Q. Liu, “3D Hyperintegration and Packing Technologues for Micro-Nano Systems,” Proc. IEEE, pp. 18--30, Jan. 2009.
[3] Mark Miller, ”Manufacturing-aware design helps boost IC yield”, EE Times, Sep. 2004.
[4] A. Agatwal, H. Sampath, V. Yelamanchili and R. Vemuri, “Fast and Accurate Parasitic Capacitance Models for Layout-Aware Synthesis of Analog Circuit” 41st Design Automation Conference, 2004.
[5] National Semiconductor, ”Power ”High-Performance Analog Seminar 2007.
[6] C. Y. Wang “A Current-Mode Buck Regulator with an Adjusted-Slope Compensation Ramp , ” NCKU MS. Thesis, 2005
[7] S.H.M. Ali, P.R. Wilson, and A.D. Brown, "Yield Predictive Model Characterization In Analog Circuit Design", International Symposium on Integrated Circuits, pp. 289 - 292, 2007.
[8] Del Mar Hershenson, M., "CMOS analog circuit design via geometric programming," American Control Conference, pp. 3266 – 3271, Vol.4, 2004.
[9] W. Daems, G. Gielen, and W. Sansen, "Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 517 - 534, Vol. 22, Issue:5, 2003.
[10] P. Mandal, and S. Maji , ”A CAD methodology for automatic topology selection & sizing”, SOCC, 2011.
[11] S. DasGupta, and P. Mandal , “An automated design approach for CMOS LDO regulators”, ASP-DAC , 2009.
[12] S.-H. Chen, K.-C. Chu, J.-Y. Lin, C.-H. Tsai, “DFM/DFY Practices During Physical Designs for Timing,” Asia and South Pacific Design Automation Conference, pp. 232-237, 2007.
[13] M. Bühler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath, A. Ripp, “DFM/DFY Design for Manufacturability and Yield - Influence Of Process Variations in Digital, Analog and Mixed-Signal Circuit Design,” Design Automation and Test in Europe, pp. 1-6, 2006.
[14] X. Li, J. Wang, L. T. Pileggi, T.-S. Chen, W. Chiang, “Performance-Centering Optimization for System-Level Analog Design Exploration,” International Conference on Computer-Aided Design, pp. 422-429, 2005.
[15] H. E. Graeb, “Analog Design Centering and Sizing,” Springer, 2007.
[16] Y.-S. Shyu, “Low Operating Current Analog Integrated Circuits,” Ph.D Dissertation, National Chiao Tung University, Taiwan, 2002.
[17] G. A. Rincon-Mora, “Current Efficient, Low Voltage, Low Dropout Regulators,” Ph.D. Dissertation, Elect. Comp. Eng. Dept., Georgia Inst of Technol., Atlanta, 1996.
[18] B. S. Lee, “Technical Review of Low Dropout Voltage Regulator Operation and Performance,” Application Report, Aug. 1999.
[19] 詹立宇, "可改善幾何演算法之精準度的電壓趨動運算放大器自動化設計方法," 國立中央大學電機工程研究所碩士論文, July 2011
[20] 李孟蓉, “建立精準的鎖相迴路行為模型來快速分析製程漂移之影響,” 國立中央大學電機工程研究所碩士論文, Jul. 2006
[21] Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, and Ching-Ji Huang, "Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models," IEEE Transactions on Circuits and Systems I, vol. 56, no. 6, pp. 1160-1 172, June 2009.
[22] 王裕謙,“以行為模型建立鎖相迴路之非理想現象的研究,” 國立中央大學電機工程研究所碩士論文, Jun. 2004.
[23] 郭晉誠, “建立考慮電源雜訊之鎖相迴路行為模型,” 國立中央大學電機工程研究所碩士論文, Jun. 2005.
[24] H. Habal and H. Graeb, “Constraint-Based Layout-Driven Sizing of Analog Circuits,” IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, no.8 , pp.1089-1102 , AUG. 2011
[25] B. Razavi, “Design of analog CMOS integrated circuits,” McGraw-Hill Higher Education, 2001
[26] Custom Design Tools Laker form Synopsys, http://www.synopsys.com
[27] C. Flynt, M. Kaufmann “TCL/TK A Developer’s Guide,” May. 2003.
[28] C.-L. Hsu, “A Template-Based Layout Automation Tool for PLL Circuits,” M.S. thesis, Central University, Taiwan, 2011.
[29] F. Maloberti, “Layout of Analog CMOS IC,” June. 2011
[30] C.-L. Hsu, “A Template-Based Layout Automation Tool for PLL Circuits,” M.S. thesis, Central University, Taiwan, 2011.
[31] H.-Y. Luo, H.-W. Li, L.-C. Yeh, C.-N. J. Liu, "Automated Synthesis Design Flow of Power Converter Circuits Aimed at SOC Applications", IEEE International Symposium on Integrated Circuits (ISIC), 2011.
[32] G. A.Rincon-Mora, “Current Efficient, Low Voltage, Low Dropout Regulators,” Ph.D. Dissertation, Elect. Comp. Eng. Dept., Georgia Inst of Technol., Atlanta, 1996.
[33] T. McConaghy, G. G. E. Gielen, “Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1627-1640, 2009.
[34] F. Liu, S. Ozev, “Hierarchical analysis of process variation for mixed-signal systems,” Asia and South Pacific Design Automation Conference, vol.1, pp. 465-470, 2005.
[35] Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Liu, Tai-Chen Chen,”LASER: layout-aware analog synthesis environment on laker”, Great lakes symposium on VLSI (GLSVLSI),May 2–3, 2013
[36] Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu , “Simultaneous optimization for low dropout regulator and its error amplifier with process variation”, VLSI Design, Automation and Test, 2014.
[37] A. Agarwal and R. Vemuri, “Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners,” IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), 2005
[38] Y.-C. Ding, “Template-Based Parasitic-Aware Synthesis Approach forAnalog Circuits,” M.S. thesis, Central University, Taiwan, 2012.
[39] Y.-L. Chen, W.-R. Wu, C.-N.J. Liu, J.C.-M. Li, “Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, Jan. 2014
[40] 潘財明,”低電源雜訊之電流模式低壓降穩壓器,” 國立台北科技大學電子電腦與通訊產業研發碩士專班碩士學位論文,July 2007.

指導教授

劉建男(Chien-Nan Liu)

審核日期

2014-8-27

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