具調適性頻率與責任週期之穩態視覺誘發電位大腦人機介面 ― FPGA為基礎之全系統設計

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姓名

邱韻仁(Yun-jen Chiu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具調適性頻率與責任週期之穩態視覺誘發電位大腦人機介面 ― FPGA為基礎之全系統設計
(Total Design of an FPGA-Based Brain Computer Interface with Adaptive Frequency and Pulse Duty-cycle Stimuli Tuning Design)

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摘要(中)

本論文致力於設計一套只需使用三個電極的穩態視覺誘發電位(steady state visual evoked potentials, SSVEP)大腦人機介面(brain-computer interface, BCI)。不同於一般利用商業性產品架構出來的大腦人機介面，本論文提出一套利用場可程式邏輯閘陣列(field programmable gate array, FPGA)為基礎之全系統設計。此外本論文還將採用自適性閃爍頻率調整策略來提高不同使用者於操作系統時的效率，並結合脈衝責任周期的調整來提高穩態視覺誘發電位的強度，這個部分很少被其他論文所討論。雖然低頻的閃光訊號可以誘發出較明顯的穩態視覺誘發電位，但是低頻的閃光容易造成使用者的不適與疲憊，因此本系統採用中高頻率來設計閃爍光源。
此系統使用以發光二極體(light-emitting diode, LED)為閃爍光源的閃光面板來誘發使用者的穩態視覺誘發電位。另外還將設計一套穩態視覺誘發電位放大擷取電路與一套以場可程式邏輯閘陣列為基礎之訊號處理系統來處理所擷取到的腦電訊號(electroencephalography, EEG)。在系統架構上，採用三模式型態來實現完整的訊號處理流程；此三組模式分別為閃光頻率/責任週期選擇模式、校正模式或應用模式。其中的閃光頻率/責任週期選擇模式主要用於找出於24到36 Hz中適合使用者使用的兩個最佳頻率與配合此頻率的適當責任週期。當完成閃光頻率/責任週期選擇模式後，此系統會切換到校正模式與應用模式，讓使用者可以開始利用此閃光面板來操作周遭的電器。此外本系統使用相位編碼技術來擴展單頻/單命令為單頻/多命令。最後實驗結果顯示此論文提出的系統有良好的性能，在平均正確率上高達95%，且平均單一命令產生時間(command transfer interval, CTI)為4.4925秒。

摘要(英)

This dissertation aims to design a steady state visual evoked potentials (SSVEP) based brain-computer interface (BCI) system with only three electrodes. Different from most BCI systems integrating commercial peripherals only to verify their feasibility, this dissertation provides a total solution design based on field programmable gate array (FPGA). First of all, this dissertation proposes a strategy to adjust the stimuli frequency for each user in order to evoke better SSVEP. To further enhance the SSVEP, duty-cycle design in stimuli is considered. However, it has been discussed less for SSVEP-based BCI systems. Though, the low frequency flickering induces more intensive SSVEP, it might make users feel uncomfortable and easily tired. Therefore, this study applies middle/high frequency flickering stimulus to solve this issue.
The system presents a light-emitting diode (LED) stimulation panel to effectively induce user’s SSVEP signal which is used as the input signal of the proposed system. Then, an SSVEP-amplifier/filter circuit and an FPGA-based SSVEP signal processor are respectively designed to acquire and process the subject’s electroencephalography (EEG). In the signal processing structure, this proposed system consists of three modes, flicker frequency/duty-cycle selection mode, calibration mode and application mode. The flicker frequency/duty-cycle selection mode obtains two best frequencies between 24 and 36 Hz with their related optimal duty-cycles. Then the system goes into the calibration and application modes to control the devices. Furthermore, the phase coding technology is used to extend the one command/one frequency to multi command/one frequency. Experimental results show the proposed system has good performance with average accuracy 95% and average command transfer interval (CTI) 4.4925 seconds per command.

關鍵字(中)

★ 穩態視覺誘發電位
★ 大腦人機介面
★ 場可程式邏輯閘陣列

關鍵字(英)

★ steady-state visual evoked potential (SSVEP)
★ brain computer interface (BCI)
★ field programmable gate array (FPGA)

論文目次

摘要. I
ABSTRACT III
誌謝. V
CONTENTS VII
LIST OF FIGURES IX
LIST OF TABLES XII
1. CHAPTER I INTRODICTION 1
1.1 Background and Motivation 1
1.2 Objectives of Dissertation 2
1.3 Survey of Previous Work 4
1.4 Organization of Dissertation 6
2. CHAPTER II THE PROPERTIES OF SSVEP 7
2.1 Physiological Background 7
2.2 Frequency Response 8
2.3 Duty-cycle Response 11
2.4 Phase Response 18
2.5 Summary 22
3. CHAPTER III THE SSVEP-BASED BCI SYSTEM 25
3.1 Structure of the SSVEP-based System 26
3.2 Design of SSVEP-amplifier/filter circuit 32
3.2.1 Electrodes 33
3.2.2 Pre-Amplifier 34
3.2.3 Band-Pass Filter 35
3.2.4 Notch Filter 36
3.2.5 Post-Amplifier and Output Adjustment 37
3.2.6 Automatic Notch Filter and Output Adjustment Control 37
3.3 SSVEP Signal Processing Algorithms 39
3.3.1 Reference Voltage Generator 39
3.3.2 IIR Band-Pass Filter 40
3.3.3 Frequency Discrimination Algorithm 41
3.3.4 Phase Discrimination Algorithm 42
3.4 Summary 45
4. CHAPTER IV HARDWARE IMPREMENTATION OF SSVEP-BASED BCI SYSTEM 47
4.1 Hardware Design and Implementation 47
4.1.1 Stimulation Panel 47
4.1.2 SSVEP-amplifier/filter circuit 50
FPGA Module Board 51
4.2 FPGA Implementation for SSVEP Signal Processing 53
4.2.2 IIR Band-Pass Filter 56
4.2.3 Workflow of SSVEP Signal Processing 57
4.3 Experimental Results 59
4.4 Summary 65
5. CHAPTER V 67
5.1 Conclusion 67
5.2 Future Work Discussion 68
REFERENCE 71

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指導教授

徐國鎧(Kuo-kai Shyu)

審核日期

2014-12-24

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