具可關閉數位控制式自我斜率偵測機制 之低功率適應性等化器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：47

、訪客IP：52.15.63.145

姓名

李曼如(Man-Ju Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具可關閉數位控制式自我斜率偵測機制之低功率適應性等化器
(A Low-power Adaptive Equalizer with Closeable Digital-control Self-slope Detection)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

近年來由於網路和處理器的快速發展，使得快速傳輸大量資料成為傳輸系統的主要動機，因此傳統的平行匯流排逐漸的被高速串列傳輸系統所取代。但是，當系統的操作頻率在億兆赫茲時，高頻的資料經過通道之後會失真及衰減。為了迎合電子產品低成本和低功率的需求，本論文提出一個具可關閉自我斜率偵測機制之低功率低成本適應性等化器來補償通道的損失。
為了降低功率消耗和面積成本，除了數位化，最有效的方法是減少和關閉高速電路，所以提出了串列處理的想法來減少高速檢測電路，這個主要的概念是使用自我斜率偵測器去偵測兩個連續的斜率，而不是傳統利用截剪器(Slicer)再使用檢測電路去偵測兩個平行斜率，而此概念詳細的作法就是將整個包含控制電路的偵測電路數位化並使用邏輯電路和暫存器來實現。補償完畢後，關閉機制會關閉偵測電路和數位控制電路來減少功率消耗。而且使用串列處理，訊號會經過相同的電路和相同的路徑，可以避免擺幅不平衡的問題或是走線不匹配的問題。
本晶片以 TSMC 90-nm 1P9M CMOS 製程來實現，在工作電壓為1-V，並關閉偵測機制時，其功率消耗為 4.35-mW (不含輸出緩衝器)，當晶片包含焊墊(Pad)時，晶片總面積為 0.6724-mm2，而核心部分的面積為 0.1-mm2 (不含輸出緩衝器)。在經過1.3公尺的通道，輸入5-Gb/s PRBS31的訊號時，輸出峰對峰的抖動量為0.28-UI。

摘要(英)

In recent years, due to rapid developments of the network and the processor, transmitting a lot of data becomes the main motivation of transmission system. Therefore, the conventional parallel bus is replaced by the high-speed serial link transmission system gradually. However, when system operates at gigahertz level frequency and the signal passes through the channel, the high frequency signal distorts and degrades. For demand of low cost and low power consumption for the consumer electronic products, this research proposes a low-power adaptive equalizer with closeable digital-control self-slope detection to compensate channel loss.
In order to reduce both power and cost, in addition to digitizing, the most effective ways are reducing and closing the high-speed circuit. The idea of serial processing is proposed to reduce one high speed detection circuit. The main concept is using the self-slope detection circuit which compares two continuous serial slopes by itself instead of the conventional detection circuit which uses slicer. The proposed detection circuit, including control circuit, is digitizing and using the register and the logic circuit. After compensation, the shutdown mechanism turns the control circuit off to reduce power. By serial processing, the data passes the same circuit and the same path to avoid swing balancing issue and mismatch.
The equalizer chip is implemented in TSMC 90-nm 1P9M CMOS technology. The equalizer works at supply power 1-V with 4.35-mW (excluding the output buffer) enabled shutdown mechanism. The total chip area is 0.6724-mm2 with pads, and the core area is 0.023-mm2 (excluding output buffer). The measured peak-to-peak jitter is 2.55-UI at 5-Gb/s by PRBS31 pattern through a 1.3-m channel.

關鍵字(中)

★ 等化器
★ 數位
★ 低功率
★ 自我斜率偵測機制
★ 適應性

關鍵字(英)

★ Low-power
★ Equalizer
★ Digital
★ Self-slope Detection
★ Adaptive

論文目次

摘要 i
Abstract ii
致謝 iii
Contents iv
Figure Captions vii
Table Captions x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Introduction to the High-speed Serial Transmission Systems 2
1.3 Thesis Organization 4
Chapter 2 Basics of Transmission System 5
2.1 Basic Concepts 5
2.1.1 Random Binary Sequence 5
2.1.2 8b/10b Encoding 6
2.1.3 Effect of Bandwidth Limitation on Data 7
2.1.4 Transmission-line Theory[2] 8
2.2 Jitter 16
2.2.1 Random Jitter 16
2.2.2 Deterministic Jitter 16
2.3 Eye Diagram 18
Chapter 3 Architecture of Equalizer 20
3.1 Equalizer Development 20
3.2 Architecture of Equalizer 23
3.2.1 Conventional Equalizer [5] 23
3.2.2 Enhancing Swing Control Technique [7] 25
3.2.3 Spectrum-balancing Technique [8] 26
3.2.4 Slope-detecting Technique [10] 27
3.3 Comparison and Discussion 28
Chapter 4 A Low-power Adaptive Equalizer with Closeable Digital-control Self-slope Detection 29
4.1 Architecture of the Self-slope Detection Circuit 29
4.2 Architecture of Equalizer 32
4.3 Behavior Analysis [10] 33
4.4 Component Parts 37
4.4.1 Equalizing Filter 37
4.4.2 Self-slope Detection Circuit 39
4.4.3 Timing Amplifier[11] 40
4.4.4 Control Unit 42
4.4.4.1 Digital Control Mechanism 42
4.4.4.2 Shutdown Mechanism 43
4.4.4.3 Delay Chain Method TDC [12] 44
4.4.4.4 Vernier Ring Oscillator Based TDC [13] 45
4.4.4.5 Up/down Counter [14] 46
4.5 Simulation Result 47
4.5.1 Channel Model 47
4.5.2 1.3-m Channel in TT corner at 50°C 49
4.5.3 1.3-m Channel in FF corner at 0°C 50
4.5.4 1.3-m Channel at SS 100°C 51
4.5.5 1.5-m Channel at SS 100°C 52
Chapter 5 Layout and Measurement 55
5.1 Layout Consideration 55
5.2 Microphotograph and Measurement Environment Setup 57
5.3 Measurement Result 60
Chapter 6 Conclusions and Future Works 72
6.1 Conclusions 72
6.2 Future Works 72
Reference 73

參考文獻

[1] B. Razavi, Design of Integrated Circuits for Optical Communications. McGraw-Hill: Behzad Razavi, 2003.
[2] S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design. John-Wiley, 2000.
[3] J. Hancock, ”Identifying Sources of Jitter ” 2004.
[4] J. T. Stonick, G. Y. Wei, J. L. Sonntag, and D. K. Weinlader, ”An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-um CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 38, pp. 436-443, Mar. 2003.
[5] J. N. Babanezhad, ”A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), May 1998, pp. 343-346.
[6] J. S. Choi, M. S. Hwang, and D. K. Jeong, ”A 0.18-um CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method,” IEEE J. Solid-State Circuits (JSSC), vol. 39, pp. 419-425, Mar. 2004.
[7] S. Gondi and B. Razavi, ”Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers,” IEEE J. Solid-State Circuits (JSSC), vol. 42, pp. 1999-2011, Sep. 2007.
[8] J. Lee, ”A 20-Gb/s Adaptive Equalizer in 0.13-um CMOS Technology,” IEEE J. Solid-State Circuits (JSSC), vol. 41, pp. 2058-2066, Sep. 2006.
[9] H. Y. Joo and L. S. Kim, ”A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 57, pp. 228-232, Mar. 2010.
[10] D. Lee, J. Han, G. Han, and S. M. Park, ”An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer,” IEEE J. Solid-State Circuits (JSSC), vol. 45, pp. 2861-2873, Dec. 2010.
[11] M. Lee and A. A. Abidi, ”A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue,” IEEE J. Solid-State Circuits (JSSC), vol. 43, pp. 769-777, Apr. 2008.
[12] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, ”1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, pp. 220-224, Mar. 2006.
[13] K.-H. Cheng, J. C. Liu, C.-Y. Chang, S. Y. Jiang, and K. W. Hong, ”Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator,” IEEE Trans. Very Large Scale Integr. Syst., vol. 19, pp. 1325-1335, Jun. 2011.
[14] H. Y. Huang, J. C. Liu, and K. H. Cheng, ”All-Digital PLL Using Pulse-Based DCO,” in IEEE Int. Conf. on Electronics, Circuits and Systems, Dec. 2007, pp. 1268-1271.
[15] K. H. Cheng, Y. C. Tsai, Y. H. Wu, and Y. F. Lin, ”A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 57, pp. 324-328, May 2010.
[16] K. R. Chen, C. M. Tsai, S. K. You, A. S. Li, and W. T. Chen, ”A 10 Gb/s adaptive cable equalizer using phase detection technique in 0.13-um CMOS technology,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2012, pp. 1947-1950.
[17] H. Liu, Y. Wang, C. Xu, X. Chen, L. Lin, Y. Yu, et al., ”A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 61, pp. 1001-1011, Apr. 2014.
[18] S. Shahramian, C. Ting, A. Sheikholeslami, H. Tamura, and M. Kibune, ”A pattern-guided adaptive equalizer in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 354-356.
[19] W. S. Kim, C. K. Seong, and W. Y. Choi, ”A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 59, pp. 553-557, Sep. 2012.
[20] G. E. Zhang and M. M. Green, ”A 10 Gb/s BiCMOS adaptive cable equalizer,” IEEE J. Solid-State Circuits (JSSC), vol. 40, pp. 2132-2140, Nov. 2005.
[21] M. H. Shakiba, ”A 2.5 Gb/s adaptive cable equalizer,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1999, pp. 396-397.
[22] D. A. Johns and D. Essig, ”Integrated circuits for data transmission over twisted-pair channels,” IEEE J. Solid-State Circuits (JSSC), vol. 32, pp. 398-406, Mar. 1997.
[23] A. J. Baker, ”An adaptive cable equalizer for serial digital video rates to 400 Mb/s,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1996, pp. 174-175.
[24] M. Park, J. Bulzacchelli, M. Beakes, and D. Friedman, ”A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 230-599.
[25] S. Ruifeng, P. Jaejin, F. O′Mahony, and C. P. Yue, ”A low-power, 20-Gb/s continuous-time adaptive passive equalizer,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2005, pp. 920-923.
[26] “HSPICE User Guide: Simulation and Analysis,” Ver. C-2009.03, Mar. 2009.
[27] “PCI Express ® Base Specification,” Revision 3.0, Nov. 2010.
[28]”Universal Serial Bus 3.0 Specification,” Revision 1.0, Nov. 2008.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2015-1-23

推文