以多分子聚合物波導為基礎之單晶片光學網路研究

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陳進達(Chin-Ta Chen) 查詢紙本館藏

畢業系所

光電科學與工程學系

論文名稱

以多分子聚合物波導為基礎之單晶片光學網路研究
(Study of Polymer-Based Optical Network on Chip)

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至系統瀏覽論文 (2025-4-2以後開放)

摘要(中)

在本篇論文中，我們提出以多分子聚合物波導為基礎之單晶片光學網路的架構概念，此單晶片光學網路發展於具45 度微反射面之矽基光學平台。具矽基凹槽之矽基光學平台提供獨立的光路層與電路層，可分別應用於高速與低速(高頻傳輸線除外)的資料傳輸。光路層是由多分子聚合物波導結合矽45 度微反射面組成，其中45 度微反射面為一個垂直轉變結構提供非共平面光學耦合。為了探討以多分子聚合物波導為基礎之單晶片光學網路的光學與高速訊號傳輸特性，我們利用多分子聚合物波導結合矽45 度微反射面探討點對點及點對多點 (在本篇論文中，我們以1 分2 的光學連結為例子)的光學連結特性。
在點對點光學連結的研究中，我們利用矽45 度微反射面終止多分子聚合物波導以實現單晶片上非共平面光學耦合，其整體傳輸效率為-3.77 dB (以單模光纖為輸入端，多模光纖為輸出端)，通道間之串音小於-40 dB。此外，在輸入端與輸出端的1-dB 對準誤差容忍度可大於± 10 　um，此將易於雷射與光偵測器於矽光學平台上之封裝。為了要驗證單晶片上點對點高速訊號傳輸的能力，在本篇論文中，我們將面射型雷射/光偵測器與驅動/放大器電路及多分子聚合物波導整合至矽基光學平台上。其整體光學穿透率為 -4.7 dB (面射型雷射-波導-光偵測器經過兩個45 度微反射面)。當傳輸速度為20 Gbit/s 時，本研究架構可得到乾淨的眼圖且誤碼率優於10-12 可被達成。
關於在矽基光學平台實現以多分子聚合物波導為基礎之點對多點光學連結
研究，我們利用多分子聚合物波導結合三個矽45 度微反射面驗證晶片外光學連結之雙輸出端的光學鄰近耦合行為。雙輸出端之1-dB 的對準容忍度至少為±10μm，此有利於光纖封裝(應用於晶片外光學連結)，或光偵測器封裝(應用於晶片上光學連結)。以 1 × 2 垂直分光架構為基礎之晶片等級高速光學連結亦被實現於本篇論文。我們將雷射與兩顆光偵測器分別封裝於垂直分光架構的輸入與輸出端，其整體光學穿透率為 -3.26 dB ，兩輸出端的分光比例為1。由高速傳輸的實驗顯示，以多分子聚合物波導為基礎之1 × 2 垂直分光架構，在雷射驅動電流為3 mA 時，本研究架構可得到10-Gbit/s 眼圖。在雷射驅動電流為5 mA 時，雙輸出端的誤碼率優於10-12 也同樣被達成。此證明利用多分子聚合物垂直分光架構實現晶片等級1 × 2 光學連結是非常適合應用於單晶片上具多重輸出端之高速資料傳輸。

摘要(英)

In this dissertation, we proposed a concept of polymer-based optical network on chip (ONoC), which is developed on the silicon optical bench (SiOB) with the 45° micro-reflectors. This silicon platform with a silicon trench can provide independent photonic and electrical layers, respectively for high-speed and low-speed (except high-frequency transmission lines) data transmissions on a chip. The photonic layer is composed of the polymer waveguides and silicon 45° micro-reflectors, where the 45° micro-reflector as a vertical-transition structure is utilized for out-of-plane optical coupling. In order to study the optical and high-speed characteristics of polymer-based ONoC, its point-to-point and point-to-multipoint (1 x 2 optical interconnects as an example in this dissertation) optical links using the polymer waveguide terminated at 45° micro-reflectors are investigated step by step.
For the study of point-to-point optical interconnects based on the SiOB with the polymer waveguides, the 45°-mirror terminated polymer waveguide is realized to
demonstrate an on-chip non-coplanar optical coupling. Its total transmission of -3.77 dB (single-mode fiber (SMF) as input, multi-mode fiber (MMF) as output) and the
channel-to-channel cross talk suppressed down to -40 dB are experimentally obtained,respectively. Besides, the large 1-dB alignment tolerances for a SMF at input port and a MMF at output port can be more than ± 10 um, that will facilitate the laser and PD assembly onto the SiOB; In order to demonstrate the high-speed transmission capability of chip-level point-to-point optical interconnects, the VCSEL/ PD and the driver/amplifier IC as well as the polymer waveguides combined with the 45°
micro-reflectors are integrated on the SiOB, respectively. The total optical transmission (VCSEL-to-waveguide-to-PD via two 45° micro-reflectors) is -4.7 dB. The clear eye pattern and bit error rate (BER) better than 10-12 for the proposed architecture are successfully demonstrated, respectively as the data rate is up to 20
Gbit/s.
For the research of polymer-based point-to-multipoint optical interconnects on the SiOB, a polymer waveguide combined with three silicon 45° micro-reflectors are
realized to demonstrate a two-port optical proximity coupling of the off-chip optical interconnects based on the polymer 1 × 2 vertical splitter. The wide 1-dB alignment tolerances at least ±10 μm for two output ports are achieved, that will facilitate not only the fiber assembly for off-chip optical interconnects, also PD assembly onto the SiOB for on-chip optical interconnects with multiple output ports; The chip-level high-speed optical interconnects based on the polymer 1 × 2 vertical splitter is also demonstrated. One VCSEL and two PD chips are flip-chip assembled onto the splitter to demonstrate the point-to-multipoint high-speed optical interconnects. The total optical transmission is- 3.26 dB with a power-splitting ratio of unity. The high-speed transmission experiment shows the reasonable 10-Gbit/s eye patterns for the proposed architecture under a low bias current (3 mA) of VCSEL. The BERs better than 10-12 at two output ports under a 5-mA bias current are also achieved. It indicates that such the chip-level 1 × 2 optical interconnects using the polymer vertical splitter is
suitable for high-speed data transmission with multiple output ports.

關鍵字(中)

★ 光學連結
★ 高分子光學波導
★ 矽基光學平台

關鍵字(英)

★ optical interconnection
★ polymer waveguide
★ silicon optical bench

論文目次

Abstracts...............................................I
Abstracts in Chinese..................................III
Acknowledgements........................................V
Contents...............................................VI
Figure Lists...........................................IX
Table Lists...........................................XIV
Chapter 1. Introduction.................................1
1.1 Bottleneck of Inter- / Intra-Chip Electrical Interconnects ..........................................2
1.2 Chip-level Optical Interconnects with Laser, Waveguide, and PD Integrations on a Si (or SOI) Substrate for Optical Network on Chip.............................6
1.3 Research Topics of Polymer-based Optical Network on Chip ................................................. 12
Chapter 2. 45°-Mirror Terminated Polymer Waveguides on Silicon Substrates.....................................16
2.1. Introduction......................................16
2.2. Optical Design of 45°-Mirror Terminated Polymer Waveguide .............................................18
2.3. Realization of 45°-Mirror Terminated Polymer Waveguide .............................................20
2.4. Optical-Characteristic Evaluations of 45°-Mirror Terminated Polymer Waveguide...........................21
2.5. Summary...........................................24
Chapter 3. Two-Port Optical Proximity Coupling of Off-Chip Optical Interconnects Based on 1 × 2 Vertical Splitter ..............................................25
3.1. Introduction......................................25
3.2. Design of Two-Port Optical Proximity Coupling of Off-Chip Optical Interconnects Based on 1 × 2 Vertical Splitter...............................................28
3.3. Realization of Two-Port Optical Proximity Coupling of Off-Chip Optical Interconnects Based on 1 × 2 Vertical Splitter...............................................32
3.4. Optical Characterization of Two-Port Optical Proximity Coupling of Off-Chip Optical Interconnects Based on 1 × 2 Vertical Splitter.......................34
3.5. Summary...........................................37
Chapter 4. Chip-Level Optical Interconnects Using Polymer Waveguide Integrated with Laser/PD and Driver/Amplifier IC on Silicon .........................................38
4.1. Introduction......................................38
4.2. Realization of Chip-Level Optical Interconnects Using Polymer Waveguide Integrated with VCSEL/PD and Driver/Amplifier IC
4.2.1 Optical Design and Alignment Tolerances for Polymer Waveguide Terminated at 45° Micro-reflectors...........41
4.2.2 Fabrications of Polymer Waveguide Hybrid Integrated with 45° Micro-reflectors, and Assembly of VCSEL/PD and Driver/Amplifier IC onto a Silicon Platform............42
4.2.3 I-V Characteristics of VCSEL/PD before and after Bonding ...............................................44
4.3. Characterization of Chip-Level Optical Interconnects Using Polymer Waveguide Integrated with VCSEL/PD and Driver/Amplifier IC
4.3.1 Optical Characteristics of Polymer Waveguide Terminated at 45° Micro-reflectors.....................46
4.3.2 High-speed Characteristics of Polymer Waveguide Integrated with VCSEL/PD and Driver/Amplifier IC.......47
4.4. Summary...........................................49
Chapter 5. Chip-Level 1 x 2 Optical Interconnects Using Polymer Vertical Splitter on Silicon Substrate.........50
5.1. Introduction......................................50
5.2. Optical Design of Chip-Level 1 × 2 Optical Interconnects Using Polymer Vertical Splitter..........53
5.3. Realization of Chip-Level 1 × 2 Optical Interconnects Using Polymer Vertical Splitter..........57
5.4. Characterization of Chip-Level 1 × 2 Optical Interconnects Using Polymer Vertical Splitter
5.4.1 Simulated and Measured Scattering (S)-parameter of High-Frequency Transmission Lines......................59
5.4.2 Optical Transmission Loss and Power-Splitting Ratio of 1 × 2 Vertical Splitter.............................61
5.4.3 Small-Signal Frequency Responses of Polymer Vertical Splitter .....................................62
5.4.4 Performance of High-Speed Data Transmission of Polymer Vertical Splitter..............................63
5.5. Summary...........................................66
Chapter 6. Conclusions and Future Works................67
References.............................................72
Publication Lists..................................... 78

參考文獻

[1]. D. Vantrease et al., “Corona: System Implications of Emerging Nanophotonic Technology,” IEEE Computer Architecture, 2008. ISCA ′08. 35th International Symposium, pp. 153-164, June 2008.
[2]. M. J. R. Heck and J. E. Bowers, “Energy Efficient and Energy Proportional Optical Interconnects for Multi-Core Processors: Driving the Need for On-Chip Sources,” IEEE J. Sel. Top. Quantum Electron., vol. 20, no. 4, pp. 8201012, July 2014.
[3]. J. Howard et al., “A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 108-110, Feb. 2010.
[4]. S. Bell et al., “TILE64TM Processor: A 64-Core SoC with Mesh Interconnect,” IEEE International Solid-State Circuits Conference, pp. 88-90, Feb. 2008.
[5]. Y. Arakawa, T. Nakamura, Y. Urino and T. Fujita, “Silicon photonics for next generation system integration platform,” IEEE Communications Magazine, vol. 51, no. 3, pp. 72-77, March 2013.
[6]. S.-W. Seo, S.-Y. Cho, and N. M. Jokerst, “A Thin-Film Laser, Polymer Waveguide, and Thin-Film Photodetector Cointegrated Onto a Silicon Substrate,” IEEE Photon. Technol. Lett., vol. 17, no. 10, pp. 2197–2199, Oct. 2005.
[7]. T. Spuesens, J. Bauwelinck, P. Regreny, and D. V. Thourhout, “Realization of a Compact Optical Interconnect on Silicon by Heterogeneous Integration of III–V,” IEEE Photon. Technol. Lett., vol. 25, no. 14, pp. 1332–1335, July 2013.
[8]. T. Spuesens, F. Mandorlo, P. R.-Romeo, P. Régreny, N. Olivier, J.-M. Fédeli, and D. V. Thourhout, “Compact Integration of Optical Sources and Detectors on SOI for Optical Interconnects Fabricated in a 200 mm CMOS Pilot Line,” Journal of Light. Tech., vol. 30, no. 11, pp. 1764-1770, June 2012.
[9]. Y. Urino et al., “Demonstration of 30-Tbps/cm2 Bandwidth Density by Silicon Optical Interposers Fully Integrated with Optical Components,” 39th European Conference and Exhibition on Optical Communication (ECOC), pp. 99-101, Sep. 2013.
[10]. Y. Urino et al., “First demonstration of high density optical interconnects integrated with lasers, optical modulators, and photodetectors on single silicon substrate,” Opt. Express, vol. 19, no. 26, pp. B159-B165, Dec. 2011.
[11]. S. Akiyama et al., “12.5-Gb/s operation with 0.29-V·cm VπL using silicon Mach-Zehnder modulator based-on forward-biased pin diode,” Opt. Express, vol. 20, no. 3, pp. 2911-2923, Jan. 2012.
[12]. T. Shimizu, N. Hatori, M. Okano, M. Ishizaka, Y. Urino, T. Yamamoto, M. Mori, T. Nakamura1, and Y. Arakawa, “High-density hybridly integrated light source with a laser diode array on a silicon optical waveguide platform,” OSA Advanced Photonics Congress, paper ITu4B.5, Jane 2012.
[13]. J.-W. Shi, J.-C. Yan, J.-M. Wun, J. Chen, and Y.-J. Yang, “Oxide-Relief and Zn-Diffusion 850-nm Vertical-Cavity Surface-Emitting Lasers With Extremely Low Energy-to-Data-Rate Ratios for 40 Gbit/s Operations,” IEEE J. Sel. Top. Quantum Electron., vol. 19, no. 2, pp. 7900208, March 2013.
[14]. H. Yamada, M. Nozawa, M. Kinoshita, and K. Ohashi, “Vertical-coupling optical interface for on-chip optical interconnection,” Opt. Express, vol. 19, no. 2, pp. 698-703, Jan. 2011.
[15]. C. J. Brooks, A. P. Knights, and P. E. Jessop, “Vertically-integrated multimode interferometer coupler for 3D photonic circuits in SOI,” Opt. Express, vol. 19, no. 4, pp. 2916-2921, Feb. 2011.
[16]. W.-C. Chiu, C.-Y. Lu, and M.-C. M. Lee, “Monolithic integration of 2-D multimode interference couplers and silicon photonic wires,” IEEE J. Sel. Top. Quantum Electron., vol. 17, no. 3, pp. 540-545, May 2011.
[17]. M. Asghari and A. V. Krishnamoorthy, “Energy-efficient communication,” Nature Photonics, vol. 5 pp. 268-270, May 2011.
[18]. J. Inoue, T. Ogura, K. Kintaka, K. Nishio, Y. Awatsuji, and S. Ura, “Fabrication of embedded 45-degree micromirror using liquid-immersion exposure for single-mode optical waveguides,” Journal of Light. Tech., vol. 30, no. 11, pp. 1563-1568, June 2012.
[19]. Y. W. Xu, A. Michael, C. Y. Kwok, and G. D. Peng, “Detail study on the rear 45° micromirror smoothness on (100) Si substrates,” Procedia Engineering, vol. 5, pp. 858-861, Oct. 2010.
[20]. J.-H. Kim and R. T. Chen, “A collimation mirror in polymeric planar waveguide formed by reactive ion etching,” IEEE Photon. Technol. Lett., vol. 15, no. 3, pp. 422–424, Mar. 2003.
[21]. C.-T. Chen, P.-K. Shen, C.-C. Chang, H.-L. Hsiao, J.-Y. Li, K. Liang, T.-Y. Huang, R.-H. Chen, G.-F. Lu, and M.-L. Wu, “45°-Mirror Terminated Polymer Waveguides on Silicon Substrates,” IEEE Photon. Technol. Lett., vol. 25, no. 2, pp. 151-154, Jan. 2013.
[22]. C. T. Chen, P. K. Shen, C. C. Chang, J. Y. Li, H. L. Hsiao, Y. C. Lee, M. L. Wu, “Polymer Waveguides Based on Silicon Optical Benches” Proc. of SPIE, vol. 8264, pp. 82640G-1-6, Feb. 2012.
[23]. H. C. Lan, H. L. Hsiao, C.C. Chang, C. H. Hsu, C. M. Wang, and M. L. Wu, “Monolithic integration of elliptic-symmetry diffractive optical element on silicon-based 45° micro-reflector,” Opt. Express, vol. 17, no. 23, pp. 20938-20944, Nov. 2009.
[24]. H. L. Hsiao, H. C. Lan, C.C. Chang, C. Y. Lee, S. P. Chen, C. H. Hsu, S. F. Chang, Y. S. Lin, F. M. Kuo, J. W. Shi, and M. L. Wu, “Compact and passive-alignment 4-channel × 2.5-Gbps optical interconnect modules based on silicon optical benches with 45° micro-reflectors,” Opt. Express, vol. 17, no. 26, pp. 24250-24260, Dec. 2009.
[25]. T. Hino, R. Kuribayashi, Y. Hashimoto, T. Sugimoto, J. Ushioda, J. Sasaki, I. Ogura, I. Hatakeyama, and K. Kurata, “A 10 Gbps × 12 channel pluggable optical transceiver for high-speed interconnections,” IEEE Electronic Components and Technology Conference, pp. 1838–1843, 2008.
[26]. R. Dangel, C. Berger, R. Beyeler, L. Dellmann, M. Gmür, R. Hamelin, F. Horst, T. Lamprecht, T. Morf, S. Oggioni, M. Spreafico, and B. J. Offrein, “Polymer-waveguide-based board-level optical interconnect technology for datacom applications,” IEEE Trans. on Advan. Packag., vol. 3, no. 4, pp. 759-767, July 2008.
[27]. F. E. Doany, C. L. Schow, B. G. Lee, R. A. Budd, C. W. Baks, C. K. Tsang, J. U. Knickerbocker, R. Dangel, B. Chan, H. Lin, C. Carver, J. Huang, J. Berry, D. Bajkowski, F. Libsch, and J. A. Kash, “Terabit/s-class optical PCB links incorporating 360-Gb/s bidirectional 850 nm parallel optical transceivers,” Journal of Light. Tech., vol. 30, no. 4, pp. 560-571, Feb. 2012.
[28]. F. E. Doany, C. L. Schow, C. W. Baks, D. M. Kuchta, P. Pepeljugoski, L. Schares, R. Budd, F. Libsch, R. Dangel, F. Horst, B. J. Offrein, and J. A. Kash, “160 Gb/s bidirectional polymer-waveguide board-level optical interconnects using CMOS-based transceivers,” IEEE Trans. on Advan. Packag., vol. 32, no. 2, pp. 345-359, May 2009.
[29]. M. Immonen, M. Karppinen, and J. K. Kivilahti, “Fabrication and characterization of polymer optical waveguides with integrated micromirrors for three-dimensional board-level optical interconnects,” IEEE Trans. on Electro. Packag. Manufact., vol. 28, no. 4, pp. 304-311, Oct. 2005.
[30]. W.-J. Lee, S. H. Hwang, M. J. Kim, E. J. Jung, J. B. An, G. W. Kim, M. Y. Jeong, and B. S. Rho, “Multilayered 3-D optical circuit with mirror-embedded waveguide films,” IEEE Photon. Technol. Lett., vol. 24, no. 14, pp. 1179-1181, July 2012.
[31]. S. Hiramatsu, and T. Mikawa, “Optical design of active interposer for high-speed chip level optical interconnects,” Journal of Light. Tech., vol. 24, no. 2, pp. 927-934, Feb. 2006.
[32]. J. Chandrappan, H. Kuruveettil, T. C. Wei, C. T. W. Liang, P. V. Ramana, K. Suzuki, T. Shioda, and J. H. Lau, “Performance characterization methods for optoelectronic circuit boards,” IEEE Trans. on Comp., Packag. and Manufact. Tech., vol. 1, no. 3, pp. 318-326, March 2011.
[33]. N. Hendrickx, J. V. Erps, E. Bosman, C. Debaes, H. Thienpont, and P. V. Daele, “Embedded micromirror inserts for optical printed circuit boards,” IEEE Photon. Technol. Lett., vol. 20, no. 20, pp. 1727-1729, Oct. 2008.
[34]. W.-J. Lee et al., “Surface Input/Output Optical Splitter Film for Multilayer Optical Circuits,” IEEE Photon. Technol. Lett., vol. 24, no. 6, pp. 506-508, March 2012.
[35]. S. Bernabé, C. Kopp, M. Volpert, J. Harduin, J.-M. Fédéli and H. Ribot, “Chip-to-chip optical interconnections between stacked self-aligned SOI photonic chips,” Opt. Express, vol. 20, no. 7, pp. 7886-7894, March 2012.
[36]. C.-W. Liao, Y.-T. Yang, S.-W. Huang, and M.-C. M. Lee, “Fiber-core-matched three-dimensional adiabatic tapered couplers for integrated photonic devices,” Journal of Light. Tech., vol. 29, no. 5, pp. 770-774, Match 2011.
[37]. S.-W. Huang, K.-N. Ku, M.-C. M. Lee, M.-H. Nguyen, and F.-G. Tseng, “Integrated SU-8 prisms and microgratings for polarization-selective fiber-to-silicon waveguide coupling,” IEEE Photon. Technol. Lett., vol. 24, no. 12, pp. 1054-1056, June 2012.
[38]. A. Noriki, K. Lee, J. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi, “Through-silicon photonic via and unidirectional coupler for high-speed data transmission in optoelectronic three-dimensional LSI,” IEEE Electron Device Lett., vol. 33, no. 2, pp. 221-223, Feb. 2012.
[39]. C.-C. Chang, P.-K. Shen, C.-T. Chen, H.-L. Hsiao, H.-C. Lan, Y.-C. Lee, and M.-L. Wu, “SOI-based trapezoidal waveguide with 45° microreflector for noncoplanar optical interconnect,” Opt. Lett., vol. 37, no. 5, pp. 782-784, March 2012.
[40]. P.-K. Shen, C.-T. Chen, C.-C. Chang, H.-L. Hsiao, Y.-C. Chang, S.-L. Li, H.-Y. Tsai, H.-C. Lan, Y.-C. Lee, and M.-L. Wu, “Optical interconnect transmitter based on guided-wave silicon optical bench,” Opt. Express, vol.20, no. 9, pp. 10382-10392, April 2012.
[41]. S. H. Hwang, D. D. Seo, J. Y. An, M.-H. Kim, W. C. Choi, S. R. Cho, S. H. Lee, H.-H. Park, and H. S. Cho, “Parallel optical transmitter module using angled fibers and a v-grooved silicon optical bench for VCSEL array,” IEEE Trans. Advan. Packag., vol. 29, no. 3, pp. 457-462, Aug. 2006.
[42]. M.-L. Wu, C.-T. Chen, P.-K. Shen, T.-Y. Huang, C.-C. Chang, H.-L. Hsiao, T.-Z. Zhu, H.-C. Lan, Y.-C. Lee, and Y.-S. Lin, “Polymer-Waveguide-Based Optical Circuit With Two Vertical-Transition Output Ports Realized on Silicon Substrate for Optical Interconnects,” IEEE Photonics Journal, vol. 5, no. 3, pp. 7901108, June 2013.
[43]. C.-T. Chen, P.-K. Shen, C.-C. Chang, H.-L. Hsiao, T.-Y. Huang, T.-Z. Zhu, H.-C. Lan, Y.-C. Lee, Y.-S. Lin, and M.-L. Wu “Polymer-Based Vertically Optical Splitter with 20-Gbps Transmission Rate Realized on Silicon Substrate,” Optical Fiber Communication (OFC) Conference, OTu2C.2, March 2013.
[44]. K. Ohira, K. Kobayashi, N. Iizuka, H. Yoshida, M. Ezaki, H. Uemura, A. Kojima, K. Nakamura, H. Furuyama, and H. Shibata, “On-chip optical interconnection by using integrated III-V laser diode and photodetector with silicon waveguide,” Opt. Express, vol. 18, no. 15, pp. 15440-15447, July 2010.
[45]. M. J. R. Heck, H.-W. Chen, A. W. Fang, B. R. Koch, D. Liang, H. Park, M. N. Sysak, and J. E. Bowers, “Hybrid Silicon Photonics for Optical Interconnects,” IEEE J. Sel. Top. Quantum Electron., vol. 17, no. 2, pp. 333-345, March 2011.
[46]. P.-K. Shen, C.-T. Chen, C.-H. Chang, C.-Y. Chiu, S.-L. Li, C.-C. Chang, and M.-L. Wu, “Implementation of Chip-Level Optical Interconnect With Laser and Photodetector Using SOI-Based 3-D Guided-Wave Path,” IEEE Photonics Journal, vol. 6, no. 6, pp. 2500310, Dec. 2014.
[47]. M. Schröder, M. Bülters, C. von Kopylow, R. B. Bergmann, “Novel concept for three-dimensional polymer waveguides for optical on-chip interconnects,” J. Europ. Opt. Soc. Rap. Public., vol. 7, pp. 12027-1-4, July 2012.
[48]. P. A. Thadesar and M. S. Bakir, “Novel Photo-Defined Polymer-Enhanced Through-Silicon Vias for Silicon Interposers,” IEEE Trans. on Compo. Pack. and Manufac. Electron. Technol., vol. 3, no. 7, pp. 1130-1137, July 2013.
[49]. N. Lindenmann, G. Balthasar, D. Hillerkuss, R. Schmogrow, M. Jordan, J. Leuthold, W. Freude, and C. Koos, “Photonic wire bonding: a novel concept for chip scale interconnects,” Opt. Express, vol. 20, no. 16, pp. 17667-17677, July 2012.
[50]. T. Gu, R. Nair, and M. W. Haney, “Chip-Level Multiple Quantum Well Modulator-Based Optical Interconnects,” Journal of Light. Tech., vol. 31, no. 24, pp. 4166-4174, Dec. 2013.
[51]. S. Palit, J. Kirch, M. Huang, L. Mawst, and N. M. Jokerst, “Facet-embedded thin-film III–V edge-emitting lasers integrated with SU-8 waveguides on silicon,” Opt. lett., vol. 35, no. 20, pp. 3473-3476, Oct. 2010.
[52]. M.-Y. Zeng, C.-T. Chen, P.-K. Shen, K. Liang, C.-C. Chang, H.-L. Hsiao, H.-C. Lan, Y.-C. Lee, Y.-S. Lin, and M.-L. Wu, “10-Gbit/s On-chip Optical Interconnect Module Using Silicon-Based 45° Micro-Reflectors Terminated Polymer Waveguides,” 18th Microoptics Conference (MOC), Oct. 2013.
[53]. M. W. Haney, T. Gu, and A. P. Venkataraman, “Energy-per-bit advantages of chip-scale hybrid-integrated optical interconnects using surface-normal electro-absorption MQW modulators,” IEEE Optical Interconnects Conference, pp. 1-2, May 2013.
[54]. C.-T. Chen, P.-K. Shen, T.-Z. Zhu, C.-C. Chang, S.-S. Lin, M.-Y. Zeng, C.-Y. Chiu, H.-L. Hsiao, H.-C. Lan, Y.-C. Lee, Y.-S. Lin, and M.-L. Wu, “Chip-Level 1  2 Optical Interconnects Using Polymer Vertical Splitter on Silicon Substrate,” IEEE Photonics Journal, vol. 6, no. 2, pp. 7900410, April 2014.
[55]. C.-T. Chen, P.-K. Shen, T.-Z. Zhu, C.-C. Chang, S.-S. Lin, M.-Y. Zeng, C.-Y. Chiu, H.-L. Hsiao, H.-C. Lan, Y.-C. Lee, Y.-S. Lin, and M.-L. Wu, “Chip-level 10-Gbit/s optical interconnects using 1  2 polymer vertical splitter on silicon substrate,” Optical Fiber Communication (OFC) Conference, M2K.4, March 2014.
[56]. Y. Urino, T. Horikawa, T. Nakamura, and Y. Arakawa, “Photonics-electronics convergence system for high density inter-chip interconnects by using silicon photonics,” IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 1-4, Oct. 2012.
[57]. X. Zhang, A. Hosseini, X. Lin, H. Subbaraman, and R. T. Chen, “Polymer-Based Hybrid-Integrated Photonic Devices for Silicon On-Chip Modulation and Board-Level Optical Interconnects,” IEEE J. Sel. Top. Quantum Electron., vol. 19, no. 6, pp. 3401115, Nov./Dec. 2013.
[58]. X. Zhang, A. Hosseini, S. Chakravarty, J. Luo, A. K.-Y. Jen, and R. T. Chen, “Wide optical spectrum range, subvolt, compact modulator based on an electro-optic polymer refilled silicon slot photonic crystal waveguide,” Opt. Lett, vol. 38, no. 22, pp. 4931-4934, Nov. 2013.
[59]. R. T. Chen, L. Lin, C. Choi, Y. J. Liu, B. Bihari, L. Wu, S. Tang, R. Wickman, B. Picor, M. K. H.-Brenner, J. Bristow, and Y. S. Liu, “Fully Embedded Board-Level Guided-Wave Optoelectronic Interconnects,” Proceedings of the IEEE, vol. 88, no. 6, pp. 780-793, Jane. 2000.
[60]. C.-T. Chen, H.-L. Hsiao, P.-K. Shen, G.-F. Lu, H.-C. Lan, Y.-C. Lee, C.-C. Chang, J.-Y. Li, A. Nedle, S.-F. Chang, Y.-S. Lin, and M.-L. Wu, “Miniaturized bidirectional optical subassembly using silicon optical bench with 45-deg micro-reflectors in short-reach 40-Gbit/s optical interconnects,” Opt. Eng., vol.51, no. 11, pp. 1150051-1150058, Nov. 2012.
[61]. C.-T. Chen, H.-C. Lan, H.-L. Hsiao, P.-K. Shen, C.-C. Chang, G.-F. Lu, J.-Y. Chang, S.-L. Li, A.-N. Wen, Y.-S. Lin, M.-L. Wu, “Ultra-compact TOSA/ROSA with 40-Gbps transmission rate using silicon optical benches technology,” Conference on Lasers and Electro-Optics (CLEO), CThP6, May 2011.
[62]. C.-T. Chen, H.-L. Hsiao, C.-C. Chang, P.-K. Shen, G.-F. Lu, Y.-C. Lee, S.-F. Chang, Y.-S. Lin, M.-L. Wu, “4 channels x 10-Gbps optoelectronic transceiver based on silicon optical bench technology,” Proc. of SPIE, vol. 8267, pp. 82640D-1-6, Feb. 2012.
[63]. “NRZ Bandwidth HF-Cutoff v.s. SNR”, Application Note (HFAN-09.0.1) of MAXIM, 2001.
[64]. K. Bergman, L. P. Carloni, A. Biberma , J. Chan , G. Hendry, “Photonic Network-on-Chip Design,” Book, 2014. Website: http://www.springer.com/gp/book/9781441993342#

指導教授

伍茂仁、林祐生(Mount-Learn Wu Yo-Shen Lin)

審核日期

2015-5-13

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