可靠度導向之類比積體電路擺置

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姓名

劉宗祐(Tsung-Yu Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

可靠度導向之類比積體電路擺置
(Reliability-Driven Placement for Analog Integrated Circuits)

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摘要(中)

由於類比電路的敏感性，在元件尺寸大幅地縮小之後，考量佈局後的非理想效應以及可靠度顯得更為重要。為降低非理想效應對電路效能的影響與提升可靠度，類比電路設計大多以人工的方式產生佈局，雖然使用類比設計自動化搭配工程師的佈局經驗可以取代部分人工以節省設計工作量，但眾多的佈局限制仍然是類比設計自動化發展的最大難題。
目前存在許多類比元件擺置的相關文獻，然而同時考慮到可靠度與繞線的研究卻非常稀少。為降低製程變異以及非理想效應對佈局產生的影響，一般常建立拓樸限制處理元件之間的不匹配，但是繞線仍會產生非理想效應。為減少繞線對可靠度與電路效能的影響，繞線時應避免過窄的導線寬度與導線直角轉彎所造成電子遷移的現象，以及線長過長的導線所造成的線阻、寄生電阻電容值變大與訊號延遲。因此在擺置過程中必須要精準地預留繞線空間，考慮導線斜角轉彎與較寬的導線寬度所需要的空間，以及縮短導線總線長等因素，以確保電路能達到預定規格且擁有良好的壽命。
本論文提出一個在擺置階段考量可靠度的類比自動化設計流程。擺置過程中首先針對繞線路徑、導線轉彎角與寬度較寬的導線預留空間，接著再使用二階段形狀曲線修剪技巧，留下導線總線長較短、面積較小的擺置結果，最後應用延遲決策技術產生符合規格的複數擺置結果，提供使用者良好且彈性的選擇。

摘要(英)

Due to the sensitivity of analog components, both post-layout non-ideal effects and reliability are getting important with the size shrink of components. In order to reduce the impact of non-ideal effects on circuit performance and increase the reliability, the layouts of analog circuits are often generated manually. Although some EDA tools based on designer experience are available now to reduce design efforts, the complex layout constraints are still big issues for developing EDA tools.
There are many literatures on analog placement, but the number of researches on analog placement considering both reliability and routing are few. In order to reduce the impacts on the layout caused by the process variations and non-ideal effects, topology constraints are often used to reduce the mismatch between devices. However, the non-ideal effects may still exist in the routing paths. In order to reduce the impacts from routing paths on reliability and circuit performance, narrow wires, right-angle corner bend and long wires should be avoided in the routing paths. It implies that preserving routing space accurately during placement stage is required to ensure the performance and lifetime of the circuits.
This work presents an analog placement flow for analog circuits with reliability consideration. First, proper routing space is preserved for routing paths, corner bends and wide wires. Then, a two-stage curve pruning technology is proposed to obtain the placement results with shorter wire-length and smaller area. Finally adopting deferred decision making (DDM) technique, multiple flexible solutions can be provided for designers.

關鍵字(中)

★ 實體設計
★ 類比擺置

關鍵字(英)

★ physical design
★ analog placement

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章、緒論 1
1-1 類比電路設計自動化 1
1-2 研究動機 3
1-3 問題定義 6
1-4 論文結構 7
第二章、背景知識 8
2-1 類比電路元件擺置 8
2-1-1 匹配 8
2-1-2 對稱 9
2-1-3 鄰近 10
2-2 導線對類比電路之影響 11
2-2-1 可繞度 11
2-2-2 導線長度 11
2-3 類比電路可靠度考量 13
2-3-1 導線寬度 13
2-3-2 導線轉彎角度 14
2-4 廣義分割樹 15
2-5 延遲決策技術 17
第三章、相關文獻 18
第四章、演算法流程 24
4-1 樹狀架構建置 25
4-1-1 限制條件分析 25
4-1-2 配對方程式 27
4-1-3 廣義分割樹建構流程 32
4-1-4 對稱廣義分割樹建置流程 34
4-2 形狀曲線操作流程 35
4-2-1 形狀曲線保存資訊 36
4-2-2 產生基礎曲線 38
4-2-3 擺置擴展 40
4-2-4 形狀曲線修剪流程 44
4-2-5 曲線合併及繞線資訊更新 45
4-3 複數結果挑選及元件定位 46
第五章、實驗結果及分析 47
5-1 實驗環境與電路 47
5-2 電流鏡運算放大器實驗結果 50
5-3 兩級式運算放大器實驗結果 53
第六章、結論與未來展望 56
參考文獻 57

參考文獻

[1] Chris Chu and Yiu-Chung Wong, “FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp.
70–83, Jan. 2008.
[2] Chin-Yao Chen, “Area and Maximal Wire-length Optimization of Analog ICs Layout Generator,” NCU MS Thesis, 2013
[3] Pang-Yen Chou, Hung-Chih Ou, and Yao-Wen Chang, “Heterogeneous B*-trees for Analog Placement with Symmetry and Regularity Considerations,” Proc. International Conference Computer-Aided Design, pp. 512–516, 2011.
[4] Michael Eick, Martin Strasser, Helmut E. Graeb, and Ulf Schlichtmann, “Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits, ” Proc. International Symposium on Physical Design, pp. 14–17, 2010.
[5] Helmut Graeb, “ITRS 2011 Analog EDA Challenges and Approaches,” Proc. Design Automation & Test on Europe, pp. 1150–1155, 2012.
[6] 黃弘一, “Ch03-Analog Layout Consideration,” 混合訊號積體電路佈局與分析課程講義, Jan.2001.
[7] Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, and Soon-Jyh Chang, “Routability-driven Placement Algorithm for Analog Integrated Circuits,” Proc. International Symposium on Physical Design, pp. 71–78, 2012.
[8] Po-Hung Lin and Shyh-Chang Lin, “Analog placement based on novel symmetry-island formulation,” Proc. Design Automation Conference, pp. 465–470, 2007.
[9] Po-Hung Lin and Shyh-Chang Lin, “Analog Placement Based on Hierarchical Module Clustering,” Proc. Design Automation Conference, pp. 50–55, 2008.
[10] Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, and Yao-Wen Chang “Thermal-Driven Analog Placement Considering Device Matching,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 30, no. 3, pp. 325–336, Mar. 2011.
[11] Po-Hsun Wu, Lin, M.P.-H., Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, and Bin-Da Liu, “Performance-driven Analog Placement Considering Monotonic Current Paths,” Proc. International Conference Computer-Aided Design, pp. 613–619, 2012.
[12] Jens Lienig, “An Introduction to Electromigration-Aware Physical Design,” Invited Talk, Proc. International Symposium on Physical Design, pp. 39-46, 2006.
[13] Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, and Xianlong Hong, “Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation,” Proc. Asia South Pacific Design Automation Conference, pp. 191–196, 2007.
[14] 2014 Synopsys APPs Design Contest, http://apps.cad-contest.tw
[15] Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen, “LASER – Layout-Aware Analog Synthesis Environment on Laker,” Proc. Great Lake Symposium on VLSI, pp. 107–112, 2013.
[16] Synopsys® Laker® , http://www.synopsys.com
[17] Rob A. Rutenbar, “Design Automation for Analog: The Next Generation of Tool Challenges,” 1st IBM Academy Conference on Analog Design, Technology, Modeling and Tools, IBM T.J. Watson Research Labs, 2006.
[18] Juergen Scheible and Jens Lienig, “Automation of Analog IC Layout-Challenges and Solutions,” Proc. International Symposium on Physical Design, pp. 33-40,
2015.
[19] Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, and Dick Liu, “A Corner Stitching Compliant B*-tree Representation and Its Applications to Analog Placement,” Proc. International Conference Computer-Aided Design, pp. 507–511, 2011.
[20] Hsien-Ting Tsai, “Routability-driven Placement of Analog Designs using Deferred Decision Making Technique,” NCU MS Thesis, July 2012.
[21] Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, and Wei-Zen Chen, “Fast Analog Layout Prototyping for Nanometer Design Migration,” Proc. International Conference Computer -Aided Design, pp. 517–522, 2011.
[22] Jackey Zijun Yan and Chris Chu, “DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanner,“ Proc. Design Automation Conference, pp. 161–166, 2008.

指導教授

劉建男、陳泰蓁(Chien-Nan Liu Tai-Chen Chen)

審核日期

2015-7-20

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