銻砷化鎵/砷化銦鎵穿隧式場效電晶體製作與特性研究

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姓名

高楷博(Kai-Po Kao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

銻砷化鎵/砷化銦鎵穿隧式場效電晶體製作與特性研究

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摘要(中)

穿隧式場效電晶體其載子是以能帶穿隧的方式來產生電流，在室溫條件下，次臨限斜率能小於60 mV/decade，有別於傳統金氧半場效電晶體其載子是以漂移-擴散的方式來產生電流，次臨限斜率會被kT/q所限制。
本論文所使用的磊晶為p+-i-n+摻雜的銻砷化鎵/砷化銦鎵異質結構，源極為p+銻砷化鎵，其碳元素摻雜濃度大於5 × 1019 /cm3，砷的莫耳比例為51%，銻的莫耳比例為49%；汲極為n+砷化銦鎵，其矽元素摻雜濃度大於1 × 1018 /cm3，銦的莫耳比例為53%，鎵的莫耳比例為47%，通道i層厚度為150 nm。
藉由光學曝光與濕蝕刻的方式成功製作出微米尺寸的穿隧式場效電晶體，首先進行溫度相依的電性量測，並分析出三種不同的電流產生機制，第一區為類似Shockley-Read-Hall產生與複合電流區，第二區為陷阱輔助穿隧區，第三區為直接穿隧區。把氧化鋁/氧化鉿的等效氧化層厚度由2 nm縮小到1.5 nm以提升閘極對通道的控制能力，薄膜沉積後將爐管熱退火改成快速熱退火的方法使維持良好p+-i-n+磊晶特性與介面缺陷密度，最後使用脈衝量測的方式來觀察陷阱對穿隧式場效電晶體的影響。在室溫條件下，最大導通電流由直流量測下之3.56 μA/μm提升到9.01 μA/μm，最大電流開關比由2.72 × 102提升到1.75 × 103，VDS < 0 V之負電阻的峰谷比由小於1提升到1.6，最佳次臨限斜率由298 mV/decade最佳到55 mV/decade，成功突破60 mV/decade。

摘要(英)

Tunnel field effect transistors (TFETs) is based on band-to-band tunneling (BTBT) to generate the current, and subthreshold slope (S.S.) could be less than 60 mV/decade. Unlike traditional metal oxide semiconductor field effect transistors (MOSFETs), which is based on drift-diffusion carriers to generate the current, which S.S. would be limited by kT/q.
For a hetero-epitaxial structure p+-i-n+ GaAsSb/InGaAs material was used in this study. Sourse is a heavy doped p+-GaAsSb, which is > 5 × 1019 /cm3 carbon doped, 51% arsenic and 49% antimony. Drain is a heavy doped n+-InGaAs, which is > 1 × 1018 /cm3 silicon doped, 51% indium and 49% gallium. The channel is a 150 nm undoped i-InGaAs layer.
In this study, we use optical exposure and wet etching method to fabricate the micron size TFETs. First, investigating temperature-dependent current-voltage characteristics of TFETs, which is divided into three different transport mechanisms. First region is like Shockley–Read–Hall (SRH) generation–recombination current, second region is trap- assisted tunneling (TAT) and third region is band-to-band tunneling (BTBT). Scaling the Al2O3/HfO2 effective oxide thickness (EOT) from 2 nm to 1.5 nm improves the gate control capability to channel. Using rapid thermal annealing (RTA) method to replace the furnace post-deposition annealing (F-PDA) maintains great p+-i-n+ epitaxial behavior. Finially, using pulsed I-V measurement to reduce the impact of traps to TFETs. At room temperature, the characteristics of this device could obtain the maximum on current (Ion) from 3.56 μA/μm which is measured by directly current (DC) to 9.01 μA/μm, the highest on/off current ratio (Ion/Ioff) is from 2.72 × 102 to 1.75 × 103, the peak to valley current ratio (IP/IV) of negative differential resistance (NDR) is from < 1 to 1.6, and the minimum S.S. is from 298 mV/decade to 55 mV/decade which is beyond 60 mV/decade.

關鍵字(中)

★ 穿隧式場效電晶體
★ 次臨限斜率
★ 能帶至能帶穿隧
★ 銻砷化鎵
★ 砷化銦鎵

關鍵字(英)

★ TFET
★ subthreshold swing
★ band-to-band tunneling
★ GaAaSb
★ InGaAs

論文目次

目錄
摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 xi
第一章導論 1
1.1 穿隧式場效電晶體研究發展 1
1.2 研究動機 23
1.3 論文架構 24
第二章穿隧式場效電晶體簡介 25
2.1 前言 25
2.2 穿隧電流與穿隧理論 25
2.3 江崎二極體(Esaki diode) 28
2.4 穿隧式場效電晶體操作原理 30
2.4.1 N型與P型穿隧式場效電晶體的關閉狀態 30
2.4.2 N型與P型穿隧式場效電晶體的導通狀態 31
2.5 穿隧式場效電晶體的重要參數 32
2.6 結論 33
第三章銻砷化鎵/砷化銦鎵穿隧式場效電晶體製程與改變高介電係數複合薄膜氧化層厚度的實驗特性分析 34
3.1 前言 34
3.2 銻砷化鎵/砷化銦鎵異質磊晶結構 34
3.3 穿隧式場效電晶體製程流程 35
3.4 高介電係數複合薄膜氧化層厚度之穿隧式場效電晶體特性與分析 45
3.4.1 氧化鋁/氧化鉿複合薄膜氧化層厚度為1/5 nm之穿隧式場效電晶體特性 46
3.4.2 氧化鋁/氧化鉿複合薄膜氧化層厚度為1/3.5 nm之穿隧式場效電晶體特性 61
3.4.3 不同高介電係數複合薄膜氧化層厚度之穿隧式場效電晶體特性比較 71
3.5 結論 77
第四章銻砷化鎵/砷化銦鎵穿隧式場效電晶體之高介電係數複合薄膜氧化層沉積後熱退火的實驗特性分析 78
4.1 前言 78
4.2 高介電係數複合薄膜氧化層沉積後熱退火之穿隧式場效電晶體特性與分析 78
4.2.1 高介電係數複合薄膜氧化層沉積後爐管熱退火之穿隧式場效電晶體特性 78
4.2.2 高介電係數複合薄膜氧化層沉積後快速熱退火之穿隧式場效電晶體特性 79
4.2.3 不同方式的高介電係數複合薄膜氧化層沉積後熱退火之穿隧式場效電晶
體特性比較 82
4.3 脈衝量測 87
4.4 結論 91
第五章總結與未來展望 93
參考文獻 95

參考文獻

[1] Committee, I.R., “International Technology Roadmap for Semiconductors,” 2011 Edition. Semiconductor Industry Association.
[2] Iwai, H., “Future of Logic Nano CMOS Technology,” IEEE EDS DL, IIT-Bombay, Jan. 2015.
[3] Mookerjea, S. and Datta, S., “Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications,” IEEE Device Research Conf., Santa Barbara, CA, Jun. 2008, pp. 47-48.
[4] Mookerjea, S., et al. “Experimental demonstration of 100nm channel length In0.53Ga0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications,” IEEE Electron Devices Meeting(IEDM), Baltimore, MD, Dec. 2009, pp. 1-3.
[5] Mookerjea, S., Mohata, D., Mayer, T., Narayanan, V. and Datta, S., “Temperature-Dependent I–V Characteristics of a Vertical In0.53Ga0.47As Tunnel FET,” IEEE Electron Device Letters, vol. 31, no. 6, pp. 564-566, Jun. 2010.
[6] Mohata, D.K., et al. “Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications,” IEEE Electron Devices Meeting(IEDM), Washington, DC, Dec. 2011, pp. 33.5.1-33.5.4.
[7] Mohata, D.K., et al. “Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio,” IEEE VLSI Technology (VLSIT), Honolulu, HI, Jun. 2012, pp. 53-54.
[8] Mohata, D., et al. “Barrier-Engineered Arsenide–Antimonide Heterojunction Tunnel FETs With Enhanced Drive Current,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1568-1570, Nov. 2012.
[9] Bijesh, R., et al. “Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 NearBroken-gap Tunnel FET with ION=740μA/μm,GM=700μS/μm and Gigahertz Switching Performance at VDS=0.5V,” IEEE Electron Devices Meeting(IEDM), Washington, DC, Dec. 2013, pp. 28.2.1-28.2.4.
[10] Yan Zhu, Mohata, D.K., Datta, S. and Hudait, M.K., “Reliability Studies on High-Temperature Operation of Mixed As/Sb Staggered Gap Tunnel FET Material and Devices,” IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, pp. 245-254, Mar. 2014.
[11] Rajamohanan, B., et al. “0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET,” IEEE Electron Device Letters, vol. 36, no. 1, pp. 20-22, Jan. 2015.
[12] Dewey, G., et al. “Fabrication, Characterization, and Physics of III-V Heterojunction Tunneling Field Effect Transistors (H-TFET) for Steep Sub-Threshold Swing,” IEEE Electron Devices Meeting(IEDM), Washington, DC, Dec. 2011, pp. 33.6.1-33.6.4.
[13] Tao Yu, Teherani, J.T., Antoniadis, D.A. and Hoyt, J.L., “In0. 53Ga0. 47As/GaAs0. 5Sb0. 5 Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics,” IEEE Electron Device Letters, vol. 34, no. 12, pp. 1503-1505, Dec. 2013.
[14] Xin Zhao, Vardi, A. and del Alamo, J.A., “InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs Fabricated by a Top-down Approach,” IEEE Electron Devices Meeting(IEDM), San Francisco, CA, Dec. 2014, pp. 25.5.1-25.5.4.
[15] Rui Li, et al. “AlGaSb/InAs Tunnel Field-Effect Transistor With On-Current of 78 μA/μm at 0.5 V,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 363-365, Mar. 2012.
[16] Hao Lu and Seabaugh, A. “Tunnel Field-Effect Transistors: State-of-the-Art,” IEEE Journal of the Electron Devices Society, vol. 2, no. 4, pp. 44-49, Jul. 2014.
[17] S.M. Sze and K.K. Ng, Physics of Semiconductor Devices, 3rd ed. Canada: John Wiley & Sons, Inc., 2007, ch.8.
[18] Saurabh A. Mookerjea, “Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization,” Ph.D.dissertation, Univ. of Pennsylvania, EE Dept., Philadelphia, 2010.
[19] D.G. Schlom and J.H. Haeni, “A thermodynamic approach to selecting alternative gate dielectrics,” MRS Bulletin, vol. 27, no. 3, pp. 198–204, 2002.
[20] G.D. Wilk, R.M. Wallace, and J.M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations,” Journal of applied physics, vol.89, no.10, pp.5243-5275, 2001.
[21] Qianqian Huang, et al. “Comprehensive Performance Re-assessment of TFETs with a Novel Design by Gate and Source Engineering from Device/Circuit Perspective,” IEEE Electron Devices Meeting(IEDM), San Francisco, CA, Dec. 2014, pp. 13.3.1-13.3.4.

指導教授

辛裕明(Yue-Ming Hsin)

審核日期

2015-8-4

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