化合物半導體之穿隧式場效電晶體製程與導通電流特性研究

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姓名

李冠緯(Kuan-wei Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

化合物半導體之穿隧式場效電晶體製程與導通電流特性研究
(Fabrication and On-current Characterization of Compound Semiconductor Tunnel Field Effect Transistors)

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摘要(中)

穿隧式場效電晶體由於只需低的操作電壓即可使元件運作，且擁有低的關閉漏電流和低的次臨限擺幅等優點，而成為次世代取代金氧半電晶體的一大熱門；然而傳統的矽基穿隧式場效電晶體由於矽擁有較大的能隙(約1.1 eV)，使元件特性受限於低的導通電流。III-V族材料穿隧式場效電晶體因具較低能隙寬度而有較高穿隧機率，且能保持與金氧半電晶體相近數量級的電流開關比，並同時擁有高的元件導通電流，故本論文著重於開發III-V族化合物半導體之穿隧式場效電晶體。
本論文使用了同質結構與異質結構之III-V族p-i-n摻雜材料兩種磊晶，同質結構砷化銦鎵材料之銦的成分比例為53%，鎵的比例為47%，源極為p+型砷化銦鎵；而異質結構銻砷化鎵/砷化鋁銦的能隙排列為第二型錯開能隙，由於擁有很小的有效穿隧能障，使之能產生很大的導通電流，源極為p+型砷銻化鎵。
微米尺寸穿隧式場效電晶體製程部分皆以光學曝光進行圖形定義，利用濕式蝕刻將主動區以外的區域蝕刻移除，來達成元件間的電性隔離，並探討不同沉積後熱退火方式差異。成功製作出閘極寬度為 10 μm的元件，氧化層之氧化鋁/氧化鉿EOT為2 nm，氧化層沉積後快速熱退火之元件，其77 K低溫量測下次臨限擺幅為136 mV/dec，電流開關比達2.02 × 104，汲極關閉電流為3.54 × 10-5 μA/μm。而次微米尺寸穿隧式場效電晶體部分，閘極自我對準製程已開發。

摘要(英)

Tunnel field effect transistors (TFETs) are attractive candidates to replace MOSFETs for low power application due to the ability to make device work with a lower supply voltage, without increase in OFF state currents. However, TFETs suffer from a low ON current using large bandgap silicon based materials. For this reason, III-V material based devices with high ON current have been considered. because of the high tunneling probability due to the narrow and direct bandgap. Therefore, III-V material based TFETs are studied in this thesis.
There are two different epitaxy structures used in this study. In order to achieve the tunneling operation of n-type TFET, a heavily doped In0.53Ga0.47As is dedicated for source, n+- In0.53Ga0.47As is for drain, and undoped In0.53Ga0.47As is for channel in In0.53Ga0.47As homo-junction structure. And the type-II staggered gap heterojunction leads to high ON current, which a heavily doped GaAs0.12Sb0.88 is dedicated for source, n+- In0.95Al0.05As is for drain, and undoped In0.95Al0.05As is for channel.
In this study, a wet etching method was applied to fabricate micro scale TFETs by mesa isolation etch to the InP substrate. Different annealing processes were studied for insulators including Al2O3/HfO2 (EOT of 2 nm) by ALD. The n-TFET with best current and S.S. performance is a device with drain length of 2 μm. The characteristics of this device demonstrated the lowest S.S. of 136 mV/dec, on/off current ratio of 2.02 × 104 and minimum OFF state leakage current of 3.54 × 10-5 μA/μm in low temperature measurement(77 K). Moreover, a the sub-micro TFETs fabrication with self-aligned gate technology have been developed.

關鍵字(中)

★ 穿隧式場效電晶體

關鍵字(英)

★ TFET

論文目次

目錄
摘要 i
Abstract ii
目錄 i
圖目錄 iii
表目錄 vi
第一章導論 1
1.1 穿隧式場效電晶體相關研究發展 1
1.2 研究動機 20
1.3 論文架構 20
第二章穿隧式場效電晶體介紹 22
2.1 前言 22
2.2 穿隧理論與穿隧電流 22
2.3 江崎二極體(Esaki diode) 25
2.4 穿隧式場效電晶體操作機制 28
2.4.1 N型及P型元件關閉狀態 28
2.4.2 N型及P型元件導通狀態 29
2.5 穿隧式場效電晶體元件特性的重要參數介紹 30
2.6 結論 31
第三章砷化銦鎵穿隧式場效電晶體製程與特性 32
3.1 前言 32
3.2 砷化銦鎵磊晶結構 32
3.3 微米尺寸穿隧式場效電晶體元件製程流程 32
3.4 高介電係數複合薄膜氧化層之元件特性與分析 39
3.4.1 沉積後爐管熱退火之高介電係數複合薄膜氧化層元件變溫量測結果 40
3.4.2 沉積後快速熱退火之高介電係數複合薄膜氧化層元件變溫量測結果 50
3.4.3 不同氧化層沉積後熱退火方式元件之特性比較 57
3.5 結論 60
第四章銻砷化鎵/砷化銦鋁穿隧式場效電晶體製程與特性 62
4.1前言 62
4.2銻砷化鎵/砷化銦鋁異質接面磊晶結構 62
4.3 微米尺寸穿隧式場效電晶體元件製程流程 63
4.4 微米尺寸穿隧式場效電晶體元件量測結果 64
4.5 次微米尺寸穿隧式場效電晶體元件製程流程開發 67
4.6 結論 72
第五章總結與未來展望 73
參考文獻 74

參考文獻

參考文獻
[1] Committee, I.R., "International Technology Roadmap for Semiconductors, " 2011 Edition. Semiconductor Industry Association.
[2] Iwai, H. "Future of nano CMOS technology." Symposium on Microelectronics Technology and Devices (SBMicro).. IEEE. 2013
[3] Jeon, Jaeseok. Advanced Relay Design and Technology for Energy-Efficient Electronics. No. UCB/EECS-2011-81. CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, 2011.
[4] Wang, P.-F., et al., "Complementary tunneling transistor for low power application. "Solid-State Electronics, 48(12): p. 2281-2286. 2004.
[5] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec” ,IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, August, 2007.
[6] Mookerjea, S., et al. "Experimental demonstration of 100nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications. " in Electron Devices Meeting (IEDM), 2009
[7] Saurabh Mookerjea, Dheeraj Mohata, Theresa Mayer, Vijay Narayanan, and Suman Datta, “Temperature-Dependent I–V Characteristics of a Vertical In0.53Ga0.47As Tunnel FET”, IEEE Electron Device Letters, vol. 31, no. 6, pp. 564-566, June, 2010.
[8] D. K. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V.
Narayanan,J. M. Fastenau, D. Loubychev, A. K. Liu and S. Datta, “Demonstration of MOSFET-Like On-Current Performance in Arsenide/Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications”, IEEE International Electron Devices Meeting (IEDM) , pp. 33.5.1-33.5.4, 2011.
[9] Bijesh, R., et al. "Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 NearBroken-gap Tunnel FET with ION=740μA/μm,GM=700μS/μm and GigahertzSwitching Performance at VDS=0.5V. "in Electron Devices Meeting (IEDM), 2013
[10] Li, R., et al., "AlGaSb/InAs tunnel field-effect transistor with on-current of 78 at 0.5 V. "Electron Device Letters, 33(3): p. 363-365. 2012.
[11] Dewey, G., et al. "Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing." in Electron Devices Meeting (IEDM), 2011
[12] Yu, T., et al., "In0. 53Ga0. 47As/GaAs0. 5Sb0. 5 Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics." Electron Device Letters, 34(12): p. 1503-1505.2013
[13] Dey, A. W.; Borg, B. M.; Ganjipour, B.; Ek, M.; Dick, K. A.; Lind, E.; Thelander, C.; Wernersson, L.-E. High-Current GaSb/InAs(Sb) Nanowire Tunnel Field-Effect Transistors. IEEE Electron Device Lett. 2013, 34, 211–213.
[14] Zeng, Yuping, et al. "Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET with HSQ Mechanical Support." (2015).
[15] Seabaugh, Alan C.,"The Tunneling Transistor"IEEE spectrum,2013
[16] Sze, S.M. and K.K. Ng, "Physics of semiconductor devices. "2006: John Wiley & Sons.
[17] Remashan, K., et al., "ZnO-based thin film transistors having high refractive index silicon nitride gate. "Applied Physics Letters, 91(18): p. 182101. 2007.
[18] Huang, Qianqian, et al. "Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.

指導教授

辛裕明(Yue-ming Hsin)

審核日期

2015-8-5

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