基於準確誤差模型之高匹配性電容陣列擺置

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姓名

程平洋(PingYang Cheng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於準確誤差模型之高匹配性電容陣列擺置
(High Matchability Capacitor Array Placement with an Accurate Mismatch Model)

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摘要(中)

類比數位轉換器與數位類比轉換器的功用在超大型積體電路的設計內佔十分重要的地位。這兩種元件使得其他邏輯運算元件能與真實世界接軌，更使超大型積體電路能融入一般人的生活並為大眾服務。然而，類比數位轉換器與數位類比轉換器內含的電容卻會因為製程階段的不匹配效應，使得這兩個元件無法正確運作。
為了修正不匹配效應，我們以新的電容擺置方法決定類比數位轉換器與數位類比轉換器內電容的擺置方式。同時，提出一個精準的誤差模型用以評估類比數位轉換器與數位類比轉換器內電容經過製程後所承受的不匹配效應。透過使用新的方法與誤差模型，實驗結果顯示，與最新研究所提出的方法相比，本論文提出的方法可以提升13%的匹配性。

摘要(英)

The usage of analog-to-digital converters (ADC) and digital-to-analog converters (DAC) is very important in many VLSI designs. These two devices connect other logic-related devices to the real world and turn into the technologies we are using today. However, during fabrication process, the capacitors in ADCs and DACs suffer from mismatch induced error which may stop the ADCs and DACs from functioning properly.
To solve the problem, we proposed a new capacitor array placement method to determine how the capacitors in ADCs and DACs should be placed. An accurate mismatch model is also proposed to estimate the mismatch induced error among the capacitors before ADCs and DACs are fabricated. With the new method and mismatch model, the experimental result showed that 13% increasing in matchability compared with the state-of-the-art method.

關鍵字(中)

★ 電容陣列
★ 擺置

關鍵字(英)

★ capacitor
★ placement

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章序論 1
1-1 簡介 1
1-2 問題定義 2
1-3 背景知識與誤差模型 3
1-3-1 電容基本理論 3
1-3-2 系統不匹配 3
1-3-3 準確的電容誤差模型 6
1-3-4 電容比例不匹配的計算 8
1-4 論文組織 9
第二章相關研究 10
2-1 共質心模型 10
2-2 圓對稱模型 11
2-3 中心對稱模型 14
2-4 擺置模型與誤差模型比較 15
第三章電容陣列擺置演算法 17
3-1 演算法概述 18
3-2 中心區域擺置 21
3-3 外圍區域擺置 23
3-3-1 外圍區域擺置之數學理論 24
3-3-2 外圍區域擺置方法 28
3-4 優化 32
第四章實驗結果 35
第五章結論 38
參考文獻 40

參考文獻

[1] Chengming He, Kuangming Yap, Degang Chen and Randall Geiger, “Nᵀᴴ order circular symmetry pattern and hexagonal tesselation: two new layout techniques cancelling nonlinear gradient,” In Proceedings of International Symposium on Circuits and Systems, Vol. 1, pp. 237 - 240, 2004.
[2] Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin and Soon-Jyh Chang, “Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits,” In Proceedings of International Conference on Computer-Aided Design, pp. 635 - 642, 2012.
[3] Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang and Soon-Jyh Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” In Proceedings of Design Automation Conference, pp. 528 - 533, 2011.
[4] DiaaEldin Sayed and Mohamed Dessouky, “Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio,” In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 576 - 580, 2002.
[5] J. Bastos, M. Steyaert, B.Graindourze and W. Sansen, “Influence of die attachment on MOS transistor matching,” In Proceedings of International Conference on Microelectronic Test Structures, pp. 27 - 31, 1996.
[6] Jwu-E Chen, Pei-Wen Luo, and Chin-Long Wey, “Yield Evaluation of Analog Placement with Arbitrary Capacitor Ratio,” In Proceedings of International Symposium on Quality Electronic Design, pp. 179 - 184, 2009.
[7] Mallik Kandala, Ramgopal Sekar, Chenglong Zhang and Haibo Wang, "A low power charge-redistribution ADC with reduced capacitor array,” International Symposium on Quality Electronic Design, pp. 44 - 48, 2010.
[8] Seong-Jin Cho, Yohan Hong, Taegeun Yoo, and Kwang-Hyun Baek, "A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array,” International Conference on ASIC, pp. 472 - 475, 2011.
[9] Xin Dai, Chengming He, Hanqing Xing, Degang Chen and Randall Geiger, “An Nᵀᴴ order central symmetrical layout pattern for nonlinear gradients cancellation,” In Proceedings of International Symposium on Circuits and Systems, Vol. 5, pp. 4835 - 4838, 2005.
[10] Yonghua Cong and Randall L. Geiger, “Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays,” In Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 47 ,Issue: 7, 585 - 595, 2000.

指導教授

劉建男、陳泰蓁(Chien-Nan Liu Tai-Chen Chen)

審核日期

2015-8-12

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