具自適應增益調整之時脈與資料回復電路

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姓名

陳廷宗(Ting-tsung Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具自適應增益調整之時脈與資料回復電路
(A Clock and Data Recovery Circuit with Adaptive Gain Control)

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摘要(中)

隨半導體產業發展與電腦相關產業的興起，資料傳輸頻寬逐漸上升，傳統並列傳輸方式漸漸被串列傳輸取代，例如DisplayPort、SATA、USB、及PCI-E 等皆使用串列傳輸介面。本論文參考DisplayPort規格實現一個時脈與資料回復電路。
本論文實現了自適應增益調整之時脈與資料回復電路，自適應增益控制電路利用抖動量測的概念與回復時脈本身的特性，分辨輸入資料當下的相位抖動屬於高頻或是低頻。藉由調整時脈資料回復電路頻寬達到高頻與低頻的資料抖動下，皆能提高抖動容忍度。本論文使用TSMC 90 nm(TN90GUTM) 1P9M製程來實現，電路操作電壓為1 V。輸入資料速率為5.4 Gbps時，回復時脈速率為2.7 GHz，抖動量為23.11 ps(p-p)。在5.4 Gbps速率下，高頻與低頻抖動容忍度改善量分別為60.9 %與81.6 %。功率消耗為24.8 mW，晶片面積為1260 1178 um2，核心電路部分面積則為323 329 um2。

摘要(英)

In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, and PCI-E. This study presents a clock and data recovery (CDR), and takes the DisplayPort specification as reference material.
In this thesis, a CDR with adaptive gain control is proposed. The adaptive gain control circuit measures the jitter of recovered clock to detect the input data implied high-frequency or low-frequency jitter at the moment. By adjusting the bandwidth of data recovery loop, the clock and data recovery circuits can improve jitter tolerance at high-frequency and low-frequency. At 5.4 Gbps data rate, CDR jitter tolerance improvement is 60.9 percent at high-frequency, and 81.6 percent at low-frequency. This proposed was implemented by TSMC 90 nm (TN90GUTM) 1P9M process with 1 V supply voltage. When input data rate is at 5.4 Gbps, the recovered clock rate is 2.7 GHz. The period jitter of the output recovered clock is 23.11 ps (p-p). The power consumption of the CDR is 24.8 mW. The chip area is 1260 1178 um2 and the core area is 323 329 um2.

關鍵字(中)

★ 自適應增益控制
★ 時脈與資料回復電路
★ 抖動量測

關鍵字(英)

★ Adaptive Gain Control
★ CDR
★ Jitter Measurement

論文目次

摘要 i
Abstract ii
目錄 iv
圖目錄 viii
表目錄 xii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章時脈與資料回復電路之抖動考量 5
2.1 時脈抖動簡介 5
2.2 定量性抖動(DJ) 6
2.2.1 資料相關抖動(DDJ) 6
2.2.2 責任週期失真(DCD) 7
2.2.3 週期性抖動(PJ) 8
2.3 隨機性抖動(RJ) 9
2.4 眼圖分析 10
2.5 誤碼率 11
2.6 時脈與資料回復電路的抖動函數 14
2.6.1 抖動轉移函數 14
2.6.2 抖動容忍度 15
第3章時脈資料回復電路背景簡介 17
3.1 時脈與資料回復電路簡介 17
3.1.1 串列傳輸與並列傳輸 18
3.1.2 資料型態 18
3.2 取樣速率 19
3.3 傳統時脈與資料回復電路 20
3.3.1 鎖相迴路式時脈與資料回復電路 20
3.3.2 混合鎖相迴路/延遲鎖相迴路式時脈與資料回復電路 22
3.3.3 超取樣式時脈與資料回復電路 23
3.3.4 相位選擇式時脈與資料回復電路 24
3.4 提高抖動容忍度設計 25
3.4.1 雙增益路徑之超取樣式時脈與資料回復電路 25
3.4.2 自適應迴路增益之時脈與資料回復電路 26
第4章具自適應增益調整之時脈與資料回復電路 29
4.1 電路架構 29
4.2 操作說明 31
4.3 系統分析 35
4.3.1 頻率資訊鎖相迴路系統分析 35
4.3.2 時脈資料回復迴路系統分析 39
4.4 行為模型(Behavior model) 44
4.5 子電路介紹 46
4.5.1 自適應增益控制電路(Adaptive Gain Control Circuit) 46
(a) 相位偵測器(PD) 47
(b) 相位累加器(Counter) 47
(c) 偵測窗格(Detect Window) 48
4.5.2 相位頻率偵測器(PFD) 49
4.5.3 電荷幫浦(Charge Pump) 50
4.5.4 壓控振盪器(VCO) 52
4.5.5 頻帶選擇器(Band Selector) 55
4.5.6 鎖定偵測器(Lock Detector) 58
4.5.7 迴路濾波器(LF) 59
4.5.8 除頻器(Divider) 60
4.5.9 半速率二進位相位偵測器(Half-rate BBPD) 61
4.5.10 電壓電流轉換器(V/I) 63
4.6 模擬結果 65
4.6.1 時脈資料回復迴路控制電壓模擬結果 65
4.6.2 時脈資料回復迴路眼圖模擬結果 66
4.6.3 時脈資料回復迴路結果整理 68
第5章晶片佈局與量測 69
5.1 電路佈局 69
5.1.1 晶片封裝 70
5.1.2 佈局規劃與電源規劃 72
5.2 量測考量 73
5.2.1 量測環境 73
5.2.2 印刷電路板 74
5.2.3 輸入緩衝器 75
5.2.4 輸出緩衝器 76
5.3 晶片與印刷電路板照相 77
5.4 量測結果 78
5.4.1 頻率資訊鎖相迴路量測 78
5.4.2 資料回復迴路量測 79
5.4.3 抖動容忍度曲線量測 84
5.5 規格比較表 85
第6章結論 87
6.1 未來研究方向 87
參考文獻 89

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指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2015-8-20

推文