整合類比數位轉換與二維離散小波轉換於視訊 影像處理的系統晶片設計

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姓名

謝慶發(Chin-Fa Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

整合類比數位轉換與二維離散小波轉換於視訊影像處理的系統晶片設計
(A SoC Integrating ADC and 2DDWT for Video/Image Processing)

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摘要(中)

行車紀錄系統與監控系統均會呈現多個畫面，同時顯示在一螢幕上，此需具有影像縮小之功能。為了作系統整合之考量，若能將此縮小影像之功能與類比數位轉換器整合成一晶片，則可簡化系統設計之複雜度，本文以此為目的提出類比數位整合之系統晶片(System on a Chip, SoC)設計。

在二維離散小波轉換(2-Dimensional Discrete Wavelet Transform)的設計中，記憶體對其效能的評估具有重要之角色，傳統的二維離散小波轉換設計中需動態記憶體去儲存輸入影像與記憶體儲存行列轉換間之暫時資料，類比數位轉換器(analog-to-digital converter )為攝影模組之基本模組，本論文提出一整合類比數位轉換器與高記憶體使用效能的二維離散小波轉換系統晶片設計供視訊/影像處理用，後者僅包含列處理器和行處理器兩個主要模組。在行處理器中使用內部環型移位暫存器（Internal Ring Shift Registers,IRSR），所提出的架構可以不使用動態記憶體並降低記憶體使用量，管線技術也用在二維離散小波轉換電路以縮短臨界路徑的延遲到一個加法器的時間。所提出的架構使用較少的記憶體及較簡單之控制電路而優於現有的架構，對一個N×N個圖像，就二維一階5/3上提式離散小波轉換而言，內部環型移位暫存器僅需要2N個暫存器，而不需使用傳統架構的3.5N 個記憶體，除此之外，時脈門控技術也用於內部環型移位暫存器以減少功率消耗。

所提出的2DDWT架構以Verilog HDL設計並以TSMC 0.18微米的標準元件庫合成與驗證。類比數位轉換器則以全客戶示設計而成為一個矽智財(Intellectual Property)，之後以混合模式的設計流程整合為系統晶片，本論文不需要外部記憶體，降低了由記憶體存取與數位類比晶片整合I / O腳的功耗，同時也降低了印刷電路板的大小。所提架構具有10位元解析度，可與CMOS影像感測器(CMOS Image Sensor)或其它矽智財進一步整合供以離散小波轉換為基礎之視訊編碼使用。

摘要(英)

Driving record systems and monitoring systems will display multiple pictures simultaneously on a screen, which requires a narrow function to shrink images. For the system integration consideration, if the Analog to Digital Converter and shrink image circuit can be integrated into a chip, the complexity of the system design can be simplified. Based on this motivation, the integration of analog circuit and digital circuit is presented in this work.

The memory issue plays a very important role for the performance evaluation of a design of 2-Dimensional Discrete Wavelet Transform (2DDWT). A traditional 2DDWT architecture generally needs DRAM to store the input pixel and memory to store temporary results between row and column processors. In this paper, we present a system on a chip (SoC) for video/image processing. The chip integrates an analog-to-digital converter (ADC) with a highly efficient-memory 2DDWT. The latter one contains two main components only: a row processor and a column processor. With this integrated chip plus the use of Internal Ring Shift Registers (IRSR) in the column processor, the proposed architecture can disuse the DRAM and reduce the memory. The pipelined technique is also utilized in the proposed 2DDWT to shorten the critical path to an adder delay. The proposed architecture outperforms the existing architectures in that it uses less memory size and has low control complexity. It needs only 2N register instead of a 3.5N register of traditional architectures for a one-level 2DDWT of the 5/3 Lifting-based Discrete Wavelet Transform (LDWT) in an N x N image. Besides, The clock gating technique is also applied to the IRSR for power reduction.

The proposed 2DDWT architecture is coded in VerilogHDL and the Synopsys Design Compiler is employed to synthesize the design with the standard-cell from TSMC 0.18 μm cell library for verification. The ADC is designed by a full-custom methodology, plays as an IP of the SoC. With the integrated SoC, based on the mix-mode design flow, the proposed work requires no external memory, which accordingly reduces the power consumption by memory access and I/O PADs, it also reduces the printed circuit board (PCB) size. Moreover, the proposed SoC supports the resolution of 10 bits and can easily integrate further with the CMOS image sensor (CIS) or other IPs. This, then, completes a single chip and makes ready for the application to a real-time wavelet-based video coding.

關鍵字(中)

★ 系統晶片
★ 離散小波轉換
★ 類比數位轉換器
★ CMOS影像感測器

關鍵字(英)

★ SoC
★ Discrete Wavelet Transform
★ analog-to-digital converter
★ CMOS Image Sensor

論文目次

CHAPTER 1

INTRODUCTION 1

1.1 System Overview 1

1.2 Motivation 4

1.3 Background 6

1.4 Dissertation Organization 7

CHAPTER 2

DESIGN CONSIDERATIONS 8

2.1 Choice of ADC 8

2.2 Choice Image Processor ….....………………………………………………..……10

CHAPTER 3

PRINCIPLE OF PIPELINE ADC 11

3.1 Introduction to A-to-D Converters 11

3.2 Pipelined ADC Architecture …………………………………………………..…..14

CHAPTER４

PRINCIPLE OF DWT 17

4.1 Background 17

4.2 Lifting Scheme DWT …….…………………………………………………..……20

CHAPTER 5

PROPOSED ARCHITECTURE 23

5.1 Overview 23

5.2 ADC Architectures 24

5.3 2DDWT Architectures 28

5.3.1 Row Processor 30

5.3.2 Column Processor 38

5.4 Power Design Consideration 46

5.4.1 Clock Gating 46

5.4.2 Clock Gating Register 50

CHAPTER 6

EXPERIMENTAL RESULT AND DISCUSS 53

6.1 Library Preparation 53

6.2 Experimental Result 60

6.3 Discussion 65

CHAPTER 7

CONCLUSIONS 67

REFERENCE 68

參考文獻

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指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2015-8-27

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