使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：47

、訪客IP：18.117.192.64

姓名

蔡佳銘(Chia-ming Tsai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路
(All-Digital Clock De-Skew Circuit with Adaptive Loading Using Reused Delay Measurement Technique)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文提出了一個能隨時根據輸出負載變化進行鎖定修正，並且使用重複延遲量測技術來減少電路面積的新式全數位時脈偏移校正電路。能夠隨時根據輸出負載變化進行鎖定修正這點改善了一般同步複製延遲電路只能用於固定負載的缺點，另外使用重複延遲量測技術則達成了只使用單一硬體的架構來取代掉傳統同步複製延遲電路架構中單調、重複性高、卻又佔用了大量面積的量測延遲線，進一步的減少電路面積，更加強化同步複製延遲電路面積小的優點。

本論文所實現的使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路是使用90 nm製程來製作設計，整體晶片的總面積為955 × 955 um2，其中核心電路的面積為106 × 80 um2，操作電壓為1 V，可用的操作頻率範圍為0.34 – 1.8 GHz，功率消耗在操作頻率為1.8 GHz時為6.4 mW。電路的鎖定時間為最多19個週期，鎖定後的輸出時脈訊號在各種操作頻率下最大靜態相位誤差為20.58 ps，方均根抖動量為2.42 ps，峰對蜂抖動量為18.89 ps。

摘要(英)

In this thesis, a modern all-digital clock de-skew circuit is proposed. It not only can be calibrated by itself according to the variation of output loading, but also be reduced the area by the reused delay measurement technique. The application of the conventional SMD is restricted because it can only be used with a fixed output loading, but now the proposed all-digital clock de-skew circuit is no longer be restricted because it can be calibrated by itself according to the variation of output loading. The measurement delay line of conventional SMD is monotonous, repeated, but costs a lot of area, so this study proposed the reused delay measurement technique. The reused delay measurement technique is reusing only a single unit of hardware to measure the time difference instead of using the measurement delay line, so it can cost less area and enhance the advantage of the SMD.

This study was implemented by 90 nm process. The area of whole chip is 955 × 955 um2, and the area of the core circuits is 106 × 80 um2. The supply power voltage is 1 V, and the operating frequency is 0.34 GHz to 1.8 GHz. The power consumption at 1.8 GHz is 6.4 mW. The locking time is less than 19 cycles, and the maximum of the static phase error is 20.58 ps, the rms jitter is 2.42 ps, and the peak-to-peak jitter is 18.89 ps.

關鍵字(中)

★ 全數位
★ 時脈偏移校正電路
★ 負載自適應
★ 同步複製延遲電路

關鍵字(英)

★ all-digital
★ de-skew circuit
★ adaptive loading
★ synchronous mirror delay

論文目次

摘要 i

Abstract ii

誌謝 iii

目錄 v

圖目錄 viii

表目錄 x

第1章緒論 1

1.1 研究動機與目的 1

1.2 論文架構 4

第2章同步複製延遲電路背景簡介 5

2.1 傳統式同步複製延遲電路架構[1] 5

2.2 交錯式同步複製延遲電路架構[2] 9

2.3 直接偵測時脈偏移式同步複製延遲電路[3] 10

2.4 兩階段調整式同步複製延遲電路 11

2.4.1 逐步逼近式同步複製延遲電路[4] 12

2.4.2 環型位移式同步複製延遲電路[5] 13

2.5 各種同步複製延遲電路的比較 14

第3章使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路架構與原理 15

3.1 電路架構 15

3.2 電路原理 18

第4章使用重複延遲量測技術具負載自適應之全數位時脈偏移校正電路子電路介紹 23

4.1 粗調電路介紹 23

4.1.1 邊緣偵測器 24

4.1.2 重複使用式量測延遲電路 25

4.1.3 可移位複製控制電路 28

4.1.4 可變延遲線 29

4.2 細調電路介紹 33

4.2.1 相位比較器 34

4.2.2 逐步逼近暫存器和上數下數計數器 35

4.2.3 輸出驅動器 38

4.2.4 邊界偵測器 38

第5章晶片模擬與量測 41

5.1 電路模擬 41

5.1.1 可用操作頻率範圍模擬結果 41

5.1.2 鎖定過程模擬結果 42

5.1.3 在不同輸出負載下鎖定完成後的靜態相位誤差模擬結果 47

5.1.4 輸出負載發生變化時電路回復鎖定模擬結果 47

5.2 晶片佈局 49

5.3 量測環境考量 53

5.4 晶片與印刷電路板照相 56

5.5 晶片量測結果 57

5.5.1 可用操作頻率範圍量測結果 57

5.5.2 鎖定過程量測結果 59

5.5.3 在各種操作頻率下鎖定完成後的靜態相位誤差量測結果 61

5.5.4 負載變化後回復鎖定狀態量測結果 62

5.6 規格比較 66

第6章結論與未來研究方向 69

6.1 結論 69

6.2 未來研究方向 69

參考文獻 71

參考文獻

[1] T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, and T. Okuda, "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1656 – 1668, Nov. 1996.

[2] T. Saeki, H. Nakamura, and J. Shimizu, "A 10ps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock Generator Based on an Interleaved Synchronous Mirror Delay Scheme," in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1997, pp. 109 – 110.

[3] T. Saeki, K. Minami, H. Yoshida, and H. Suzuki, "A Direct-Skew-Detect Synchronous Mirror Delay for Application-Specific Integrated Circuits," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 372 – 379, Mar. 1999.

[4] K.-H. Cheng, K.-W. Hong, C.-H. Chen, and J.-C. Liu, "A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 7, pp. 1218 – 1228, Jul. 2011.

[5] K.-H. Cheng, K.-W. Hong, C.-F. Hsu, and B.-Q. Jiang, "An All-Digital Clock Synchronization Buffer with One Cycle Dynamic Synchronizing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1818 – 1827, Oct. 2012.

[6] M.-Y. Kim, D. Shin, H. Chae, and C. Kim, "A Low-Jitter Open-Loop All-Digital Clock Generator with Two-Cycle Lock-Time," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 10, pp. 1461 – 1469, Oct. 2009.

[7] D. Sheng, C.-C. Chung, and C.-Y. Lee, "Wide Duty Cycle Range Synchronous Mirror Delay Designs," Electron. Lett., vol. 46, no. 5, pp. 338 – 340, Mar. 2010.

[8] K.-H. Choi, J.-B. Shin, J.-Y. Sim, and H.-J. Park, "An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2055 – 2063, Sep. 2009.

[9] T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, K. Koyama, Y. Fukuzo, and T. Okuda, "A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay," in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1996, pp. 374 – 375.

[10] D. Shim, D.-Y. Lee, S. Jung, C.-H. Kim, and W. Kim, "An Analog Synchronous Mirror Delay for High-Speed DRAM Application," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 484 – 493, Apr. 1999.

[11] J.-S. Chae, D. Kim, and D. M. Kim, "Wide Range Single-Way-Pumping Synchronous Mirror Delay," Electron. Lett., vol. 36, no. 11, pp. 939 – 940, May 2000.

[12] S.-J. Jang, Y.-H. Jun, J.-G. Lee, and B.-S. Kong, "ASMD with Duty Cycle Correction Scheme for High-Speed DRAM," Electron. Lett., vol. 37, no. 16, pp. 1004 – 1006, Aug. 2001.

[13] K. Sung, B.-D. Yang, and L.-S. Kim, "Low Power Clock Generator Based on Area-Reduced Interleaved Synchronous Mirror Delay," Electron. Lett., vol. 38, no. 9, pp. 399 – 400, Apr. 2002.

[14] A. M. Fahim, "A Compact, Low-Power Low-Jitter Digital PLL," in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2003, pp. 101 – 104.

[15] K. Sung and L.-S. Kim, "A High-Resolution Synchronous Mirror Delay Using Successive Approximation Register," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1997 – 2004, Nov. 2004.

[16] Y. J. Yoon, H. I. Kwon, J. D. Lee, B. G. Park, N. S. Kim, U. R. Cho, and H. G. Byun, "Synchronous Mirror Delay for Multiphase Locking," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 150 – 156, Jan. 2004.

[17] C.-L. Hung, C.-L. Wu, and K.-H. Cheng, "Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design," in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2006, pp. 283 – 286.

[18] H. Nakaya, Y. Sasaki, N. Kato, F. Arakawa, and T. Shimizu, "An Alternative Cyclic Synchronous Mirror Delay for Versatility in Highly Integrated SoC," in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2006, pp. 279 – 282.

[19] K.-H. Cheng, C.-W. Su, and S.-W. Lu, "Wide-Range Synchronous Mirror Delay with Arbitrary Input Duty Cycle," Electron. Lett., vol. 44, no. 11, pp. 665 – 667, May 2008.

[20] D. Shin, J. Song, H. Chae, and C. Kim, "A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL with a Wide Range and High Resolution DCC," IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2437 – 2451, Sep. 2009.

[21] J.-S. Wang, C.-Y. Cheng, J.-C. Liu, Y.-C. Liu, and Y.-M. Wang, "A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1036 – 1047, May 2010.

[22] K.-H. Cheng, K.-W. Hong, Y.-L. Lo, C.-L. Wu, and C.-H. Lee, "Dynamic Frequency Tracking and Phase Error Compensation Clock De-Skew Buffer," Electron. Lett., vol. 46, no. 25, pp. 1653 – 1655, Dec. 2010.

[23] Y.-S. Kim, S.-K. Lee, H.-J. Park, and J.-Y. Sim, "A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 435 – 444, Feb. 2011.

[24] S. Hoyos, C. W. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, and B. Nikolic, "A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 um CMOS," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 3, pp. 564 – 568, Mar. 2012.

[25] Y.-H. Tu, K.-H. Cheng, C.-H. Hsu, and H.-Y. Huang, "A Low Supply Voltage Synchronous Mirror Delay with Quadrature Phase Output," in Proc. IEEE Symp. Design and Diagnostics of Electronic Ciucuits & Systems, Apr. 2014, pp. 163 – 166.

[26] 許齊發, "一個新型全數位式高解析度可變責任週期之同步複製延遲電路," 在職專班碩士, 電機工程學系, 國立中央大學, 桃園市, 2009.

[27] 涂祐豪, "具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器," 碩士, 電機工程學系, 國立中央大學, 桃園市, 2010.

[28] 洪凱尉, "全數位式高解析度快速鎖定時脈同步電路之設計與實現," 博士, 電機工程學系, 國立中央大學, 桃園市, 2011.

[29] 李柏逸, "具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路," 碩士, 電機工程學系, 國立中央大學, 桃園市, 2013.

指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2015-8-28

推文