參考文獻 |
[1] J. G. Hartnett, M. E. Tobar, E. N. Ivanov, and J. Krupka “Room temperature measurement of the anisotropic loss tangent of sapphire using the whispering gallery mode technique,” IEEE Trans. on Ultrasonics, Ferroelectrics, and Frequency Control., vol. 53, no. 1, pp. 34–38, Jan. 2006.
[2] L. Lin, T.-C. Yeh, J.-Lin Wu, G. Lu, T.-F. Tsai, L. Chen, and A.-T. Xu, “Reliability characterization of chip-on-wafer-on-substrate (CoWoS) 3D IC integration technology,” Proc. IEEE Electron. Compon. and Tech., pp. 366–371, May. 2013.
[3] W. Woods, G. Wang, and H. Ding, “Microwave compact passive circuit model of isolated interconnect over a silicon substrate with a through-silicon via (TSV) ground supply network,” European Microw. Integrated Circuits Conference., pp. 342–345, Oct. 2008.
[4] Y. P. R. Lamy, K. B. J. F. Roozeboom, D. J. Gravesteijn, and W. F. A. Besling, “RF characterization and analytical modelling of through silicon vias and coplanar waveguides for 3D integration” IEEE Trans. Aadvanced Packing., vol. 33, no. 4, pp. 1072–1079, Nov. 2010.
[5] S. Spiesshoefer, L. Schaper, S. Burkett, and G.Vangara, “Z-axis interconnects using fine pitch, nanoscale through-silicon vias: process development” Proc. IEEE Electron. Compon. and Tech., vol. 1, pp. 466–471, Jun. 2014.
[6] J. V. Olmen et al., "3D stacked IC demonstration using a through silicon via first approach", Technical Digest of the International Electron Device Meeting., pp. 1–4, Dec. 2008.
[7] Z. Xu, and J.-Q. Lu, “Through-silicon-via fabrication technologies, passives extraction, and electrical modeling for 3-D integration/packaging,” IEEE Trans. Semiconductor Manufacturing., vol. 26, no. 1, pp. 23–24, Feb. 2013
[8] E.-H. Chen et al., "Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions" Proc. IEEE Electron. Compon. and Tech., pp. 1811–1814, May. 2013
[9] H. V. Jansen, J. G. E. Gardeniers, M. J. de Boer, M. C. Elwenspoek, and J. H. J. Fluitman, “A survey on the reactive ion etching of silicon,” J. Micromech. Microeng., vol. 6, pp. 14–28, Dec. 1996.
[10] B. Wu, A. Kumar, and S. Pamarthy, “High aspect ratio silicon etch: A review,” J. Appl. Phys., vol. 108, no. 5, pp. 51101–51121, Jul. 2010.
[11] F. S.-S. Chien, C.-L. Wu, Y.-C. Chou, T. T. Chen, S. Gwob, and W.-F. Hsieh, "Nanomachining of (110)-oriented silicon by scanning probe lithography and anisotropic wet etching", Appl. Phys. Lett., vol. 75, no. 16, pp. 2429–2431, Aug. 1999
[12] A. R. Djordjevic, T. K. Sarkar, and S. M. Rao, “Analysis of finite conductivity cylindrical conductors excited by axially independent TM electromagnetic field,” IEEE Trans. Microw. Theory Tech., vol. MTT-33, no. 10, pp. 960–966, Oct. 1985.
[13] G. I. Costache, M.W. Nemes, and E. M. Petriu, “Finite element method analysis of the influence of the skin effect, proximity, and eddy currents on the internal magnetic field and impedance of a cylindrical conductor of arbitrary cross section,” in Proc. Can. Electrical and Computer Engineering Conf., pp. 253–256, Sep. 1995.
[14] L. L. W. Leung, and K. J. Chen, “Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 8, pp. 2472–2480, Aug. 2005.
[15] M. E. Goldfarb and R. A. Pucel, “Modeling via hole grounds in microstrip,” IEEE Microw. Guided Wave Lett., vol. 1, no. 6, pp. 135–137, Jun. 1991. |