博碩士論文 102521013 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:12 、訪客IP:54.211.203.45
姓名 吳凱勛(Kai-Xun Wu)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於類比積體電路中的電容陣列區塊之系統變異分析
(Systematic Variation Analysis for Application of Array Block Capacitances in Analog Integrated Circuits)
相關論文
★ E2T-iSEE:應用於事件與情感狀態轉移排程器之編輯★ “偶”:具情感之球型機器人
★ 陣列區塊電容產生器於製程設計套件之評量★ 應用於數位家庭整合計畫影像傳輸子系統之設計考量與實現
★ LED 背光模組靜電放電路徑★ 電阻串連式連續參考值產生器於製程設計套件之評量
★ 短篇故事分類與敘述★ 延伸考慮製程參數相關性之類比電路階層式變異數分析器
★ 以電子電路觀點對田口式惠斯登電橋模擬實例的再分析★ 應用於交換電容ΔΣ調變電路之電容排列良率自動化擺置平台
★ 陣列MiM電容的自動化佈局★ 陣列MiM電容的平衡接點之通道繞線法
★ 氣象資訊達人★ 嵌入式WHDVI多核心Forth微控制器之設計
★ 應用於電容陣列區塊之維持比值良率的通道繞線法★ 使用於矽穿孔耦合分析之垂直十字鏈基板結構
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中) 隨著半導體製程的不斷進步,晶片上元件尺寸與導線寬度也逐漸的微縮,這樣的改變,使得元件之間的參數變異和不匹配關係加劇,也引進了許多難以控制的製程變動問題。在現今的類比積體電路中,電路的效能受到元件間的參數變異之影響,而元件的參數值又隨著各種不匹配的效應而改變。因此,如果想使電路產生預期的理想效能表現,就必須妥善的處理電路中的不匹配。

本論文模擬了對於電容元件各種不匹配的處理方法,從相關係數的角度出發,利用元件的空間相關特性,評估電容擺放的好壞,接著模擬了線性梯度效應、氧化層梯度效應、CMP效應和溫度的梯度效應,可根據想抵制的效應進行更有效率的擺放,這樣就可以達到較完美的抗系統變異電容陣列,最後在加上隨機性的不匹配效應,透過Monte Carlo method產生出均勻分佈的隨機亂數,將系統變異和隨機變異都考量之後,可模擬出更接近真實的效應,進而提升電路的良率。
摘要(英)

As the evolution of semiconductor process technology, the size of elements and the width of wires on chips are reduced. These changes result in some uncontrollable alterations of process and aggravate the mismatch and parameter variation of components. Nowadays, the performance of analog integrated circuits is influenced not only by the parameter variation of components but also by the mismatching effects. That is to say, the approach of mismatch effects becomes a critical issue for better anticipated performance.

This thesis simulated a method for improving mismatch of elements. In this method, we estimate capacitance placement by spatial correlation. Then simulated linear gradient、oxide gradient、CMP effect and temperature gradient, according to effect users want to resist to make effective placement, it will arrive to perfect capacitor array for resist of systematic variation. Finally, adding random mismatch, through Monte Carlo method generate uniformly random distributed variable, we could get truly approaching effect after considering systematic variation and random variation, and then improving yield of circuit.
關鍵字(中) ★ 電容陣列區塊
★ 系統變異分析
關鍵字(英) ★ Array Block Capacitances
★ Systematic Variation Analysis
論文目次

中文摘要 ii
Abstract iii
致謝. iv
目錄 v
圖目錄 vii
表目錄. ix
Chapter 1. 緒論 1
1.1 動機與背景. 1
1.2 論文組織. 2
Chapter 2. 電容佈局設計的概念 4
2.1 電容之簡介. 4
2.2 電容不匹配的原因. 7
2.3 電容匹配的規則. 9
Chapter 3. 電容陣列的擺放 12
3.1 共質心(Common-Centroid) 12
3.2 空間相關性(Spatial Correlation) 15
3.2.1 相關性(Correlation)與元件不匹配(Mismatch) 18
3.2.2 電容比值的變異數與分散性 20
Chapter 4. 電容的系統變異分析 22
4.1 梯度方向的影響. 22
4.2 抗梯度的電容陣列擺置 (Gradient Resist) . 24
4.3 氧化層(Oxide)梯度效應 26
4.4 化學機械研磨(Chemical Mechanical Polishing)效應 . 28
4.5 溫度的梯度(Temperature Gradient)分析 . 30
Chapter 5. 實驗及分析 31
Chapter 6. 結論 39
參考文獻 40
參考文獻 [1] P. W. Luo, J. E. Chen, C. L. Wey, L. C. Cheng, J. J. Chen and W. C.Wu,“Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 2097-2101, Nov.2008.
[2] L. Zhang, R. Raut, Y. Jiang, and U. Kleine. “Placement algorithminanalog-layout designs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp.1889–1903, Oct.2006.
[3] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp. 1433-1439, Oct 1989.
[4] A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall,2000.
[5] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill,2001.
[6] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction ofSpatialCorrelation,”IEEETrans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr.2007.
[7] M. J. McNutt, S. LeMarquis, and J. L. Dunkley,“SystematicCapacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal Solid-State Circuits, pp. 611-616, May1994.
[8] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical DesignTechniquesfor D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug1989.
[9] D. Khalil and M. Dessouky. “Automatic GenerationofCommon-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 576-580, Mar. 2002.
[10] M. F. Lan, A. Tammineedi and R. Geiger. “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, pp. 9-26, Jul. 2001.
[11] P. W. Luo, J. E. Chen, C. L. Wey, “Design Methodology for Yeild Enhancement of Switch-Capacitor Analog Integrated Circuits” IEICE Trans. Fundamantals, Vol. E94-A, No.1, Jan.2011.
[12] P. W. Luo, J. E. Chen, C. L. Wey, “Placement Optimization for Yield Improvement of Switched-Capacitor AnalogIntegratedCircuits”, IEEETrans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No.2, pp. 313-318, Feb.2010.
指導教授 陳竹一(Jwu-E Chen) 審核日期 2016-5-6
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明