摘要(英) |
As the evolution of semiconductor process technology, the size of elements and the width of wires on chips are reduced. These changes result in some uncontrollable alterations of process and aggravate the mismatch and parameter variation of components. Nowadays, the performance of analog integrated circuits is influenced not only by the parameter variation of components but also by the mismatching effects. That is to say, the approach of mismatch effects becomes a critical issue for better anticipated performance.
This thesis simulated a method for improving mismatch of elements. In this method, we estimate capacitance placement by spatial correlation. Then simulated linear gradient、oxide gradient、CMP effect and temperature gradient, according to effect users want to resist to make effective placement, it will arrive to perfect capacitor array for resist of systematic variation. Finally, adding random mismatch, through Monte Carlo method generate uniformly random distributed variable, we could get truly approaching effect after considering systematic variation and random variation, and then improving yield of circuit. |
參考文獻 |
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