具快速次諧波時序自我校正機制之注入式鎖相迴路

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林擇瑋(Ze-Wai Lin) 查詢紙本館藏

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電機工程學系

論文名稱

具快速次諧波時序自我校正機制之注入式鎖相迴路
(A Sub-harmonically Injection Locked Phase Locked Loop with Fast Self-calibrated Timing Technique)

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摘要(中)

本論文提出一個操作於2.5 GHz具有快速時序校正技術的次諧波注入式鎖相迴路，次諧波為震盪器之操作頻率除以任意整數之頻率脈波，注入式鎖相迴路的架構有許多問題可以討論，例如注入週期、注入脈波寬度與注入時序等。本論文針對注入時序的問題分析並提出解決方法，注入時序的問題嚴重影響次諧波注入式鎖相迴路的操作效能，除了劣化輸出時脈抖動(Jitter)與參考突波(Reference Spur)之外，甚至會影響迴路的穩定，因此注入時序校正的技術十分重要。調整注入時序的方法可分為電路操作時的即時調整(Adaptively Tuning)和電路開始操作前的自我校正調整(Self-calibration Tuning)，電路正常操作時，注入時序並不會有明顯的變化，因此選擇使用自我校正調整，於完成自我校正後關閉偵測電路，降低電路的功率消耗。自我校正技術因為注入時序與鎖相迴路相位的穩定有關，導致偵測等待時間過長。本論文提出一個提升自我校正速度的技巧，利用複製壓控震盪器輔助時序自我校正，可以省去等待鎖相迴路重新鎖定的過程，大幅降低時序校正所需要的時間。並實現次諧波注入式鎖定技術，提升鎖相迴路的效能，達到低相位雜訊、低時脈抖動和低參考時脈抖動的輸出時脈表現。
電路設計與佈局採用90 nm CMOS製程實現，次諧波注入式鎖相迴路的供應電壓為1V的條件下，輸出時脈為2.5 GHz。完成注入時序校正後，次諧波注入式鎖相迴路的輸出相位雜訊在1 MHz的條件下為 -105.73 dBc/Hz，參考突波為 -56.9 dBm，參考突波與主頻率的能量差為 -48.6 dBc，整個電路的功率消耗為9.71 mW，核心電路面積為0.123 mm2，整體晶片面積為1.588 mm2。

摘要(英)

In this thesis, a 2.5 GHz sub-harmonically injection locked phase locked loop (SILPLL) with fast self-calibrated timing technique is proposed. There are many issue in SILPLL, such as injection period, injection pulse width and injection timing. This study focus on the analysis of injection timing and proposed a new solution. Bad injection timing would cause many problems in the SILPLL, such as large jitter, large reference spur, and even unlocked. Adaptively tuning technique and self-calibration tuning technique was adapted to solve the injection timing problem. In SILPLL operation, the phase of injection timing would not change over time. Self-calibration tuning technique can turn off calibrated loop after finishing calibration. It would consume less power than the other. In calibration technique, it need to confront the longtime of calibration process. Because every time of tuning needs to wait the phase of phase locked loop (PLL) to stable, the calibration time was dragged. This study proposed a new self-calibrated technique with replica voltage control oscillator. It can separate self-calibrated loop from PLL and avoid disturbing PLL phase in the calibration process. This study realized a SILPLL with self-calibrated technique with low phase noise, low jitter and low reference spur.
This work is fabricated in 90 nm CMOS process with 9.71-mW power consumption. The measured phase noise at 1 MHz offset -105.7 dBc/Hz. The measured reference spur is -48.6 dBc. The measured rms jitter is 2.27 ps.

關鍵字(中)

★ 注入式鎖相迴路
★ 次諧波注入式鎖相迴路
★ 時序自我校正
★ 林擇瑋

關鍵字(英)

★ Sub-harmonically Injection Locked Phase Locked Loop
★ SILPLL
★ Self-calibrated Timing
★ Ze-Wai Lin

論文目次

目錄
摘要 i
Abstract iii
目錄 vii
圖目錄 xi
表目錄 xv
第一章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第二章次諧波注入式鎖相迴路先前技術探討 5
2.1 鎖相迴路簡介 5
2.2 次諧波注入式鎖定簡介 6
2.2.1 相位雜訊理論[3] 6
2.2.1.1 Leesson 相位雜訊模型(線性非時變)[3] 9
2.2.1.2 Hajimiri 相位雜訊模型 (線性時變模型)[4] 11
2.2.2 倍頻式延遲鎖定迴路[5] 17
2.2.3 次諧波注入式震盪器[6] 17
2.2.4 次諧波注入式鎖相迴路[6] 18
2.2.5 相位雜訊分析[7] 20
2.3 次諧波注入式鎖定迴路面臨問題與先前架構 21
2.3.1 注入時序 (Injection Timing Issue) 21
2.3.2 除數限制(Divisor limited) 27
2.3.3 參考突波 (Reference Spur) 31
2.4 預計論文規格 32
第三章具快速次諧波時序自我校正技術之注入式鎖相迴路 33
3.1 電路架構與操作 33
3.2 快速時序自我校正技術操作原理 34
3.3 鎖相迴路之操作 36
3.4 次諧波注入鎖定迴路之操作 36
3.5 全數位式注入時序自我校正迴路 39
3.6 校正流程 41
3.7 校正時間 42
3.8 次諧波注入式鎖相迴路之系統分析 42
第四章子電路架構與設計考量 45
4.1 類比式鎖相迴路之子電路設計 45
4.1.1 相位頻率偵測器(Phase Frequency Detector, PFD) 45
4.1.2 充電幫浦 (Charge Pump, CP) 47
4.1.3 類比式低通濾波器 49
4.1.4 電壓控制震盪器 50
4.1.5 除頻器 52
4.2 次諧波注入式鎖定迴路 53
4.2.1 粗調數位控制延遲線 54
4.2.2 細調數位控制延遲線 57
4.2.3 脈波產生器(Pulse Generator, PG) 58
4.3 時序校正迴路 59
4.3.1 相位偵測器 60
第五章電路模擬與晶片量測結果 65
5.1 電路模擬 65
5.1.1 鎖相迴路模擬 65
5.1.1.1 佈局前模擬 (Pre-layout Simulation) 66
5.1.1.2 佈局後模擬 (Post-layout Simulation) 67
5.1.2 全數位式自我校正迴路模擬 68
5.1.2.1 佈局前模擬 (Pre-layout Simulation) 68
5.1.2.2 佈局後模擬 (Post-layout Simulation) 69
5.1.3 次諧波注入式鎖相迴路模擬 70
5.1.3.1 佈局後模擬 (Post-layout Simulation) 71
5.1.3.2 次諧波注入式鎖相迴路系統模擬 73
5.2 電路佈局 75
5.3 晶片照相與量測環境考量 79
5.4 量測結果 85
5.4.1 鎖相迴路 86
5.4.2 時序校正之次諧波注入式鎖相迴路 87
5.4.3 鎖相迴路與次諧波注入式鎖相迴路量測結果比較 89
5.5 規格比較 91
第六章結論與未來方向 95
6.1 結論 95
6.2 未來研究方向 95
參考文獻 97

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2016-7-26

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