以節點保留方式進行壓降分析中電源網路模型化簡的方法

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姓名

吳宗岳(Tsung-Yueh Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以節點保留方式進行壓降分析中電源網路模型化簡的方法
(Node Retention Based Model Order Reduction Approach of Power/Ground Network for IR-drop Analysis)

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摘要(中)

從超大型積體電路設計一路演進到奈米時代，現今晶片設計的技術日趨複雜，連帶影響電源網路（Power/Ground Network）之尺寸大幅增加，單看供電網路上所連接的標準元件數量就已經超過百萬等級的數量，更不用說電源網路上的電阻、電容元件更是遠超過如此龐大的數量。

傳統的設計流程中，為了評估整體晶片準確的電壓、電流值，通常會在電路設計的後期階段，進行芯片封裝板的模擬（Chip-Package-Board Co-Simulation），在此階段要做到整體電源完整性的模擬需要耗費龐大的計算時間與硬體資源，若是能提供電源網路的化簡模型，便能夠大幅縮減每一次修改又模擬的時間，不僅能縮短晶片上市的時間，更能在日益縮短的產品週期中，增加重複測試的次數，加強產品的穩定性。

我們可以藉由模型降階（MOR）之技術產生化簡模型，這樣的技術過去已經發展多年，例如基於圖形的時間常數平衡化減方法（TICER），基於投影的PRIMA、稀疏隱含投影法（SIP）。在如此龐大的電源網路中，衍出而來的電壓降形成主要問題，由於電路本身稀疏的特性，本篇論文採用基於稀疏隱含投影法（SIP）演算法為基礎所實做的平台上，提出適用於電源網路的節點保留方法（Node Retention），藉此找出並保留主導整體電路的主要節點，在可接受的電壓降精準度範圍內保留最少的節點，得到盡可能小的化簡模型。由最後的實驗結果可發現，相較單純的稀疏隱含投影法（SIP）配合隨機選點保留，經由提出的方法正確的保留節點能大幅提升精確度高達138倍。

摘要(英)

As the VLSI advances into the nanometer era, modern chip design technology becomes more complex. As a result, the size of power/ground network dramatically increases; besides, the number of components connected on power/ground network is beyond millions, not to mention the number of resistances and capacitances in the power/ground network.

In the traditional design flow, in order to verify the accuracy of voltage and current in chip, the chip-package-board co-simulation is generally performed in late design stages. However, the co-simulation will cost a lot of time and computational resources. It’s necessary for us to develop a reduced core model of power/ground network to decrease the simulation time. The proposed model can not only shorten time-to-market but also strengthen the robustness of products.

We can develop the reduced core model by model-order-reduction (MOR) techniques. There are already many approaches such as graph-based methods TICER and projection-based methods PRIM and SIP. IR-drop is a major issue in such a large power/ground network causing power integrity problems. Due to the sparse characteristics of circuit, we implement the platform based on SIP in the thesis. The proposed node retention methods reserve dominant nodes in power/ground network and get reduced model as small as possible with acceptable accuracy. The experimental results shows that the proposed node retention methods can enhance accuracy up to 138 times compared to SIP with random node retention.

關鍵字(中)

★ 電壓降分析
★ 電源網路
★ 模型化減
★ 節點保留
★ 網路分析
★ 電阻電容電路

關鍵字(英)

★ IR-drop analysis
★ Power/Ground Network
★ MOR techniques
★ Node Retention
★ network analysis
★ RC circuits

論文目次

摘要 I
ABSTRACT II
致謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章、緒論 1
1-1 電源網路 1
1-2 電壓降分析 2
1-2-1 靜態電源網路分析 4
1-2-2 動態電源網路分析 5
1-3 相關研究 7
1-4 研究動機 9
1-5 論文結構 11
第二章、背景知識 12
2-1 MOR模型降階技術 12
2-2 SIP演算法背景知識 13
2-3 CHOLESKY DECOMPOSITION 16
2-4 問題定義 19
第三章、節點保留法 21
3-1 實作SIP演算法 22
3-2 以節點保留法進行SIP演算法的流程 27
3-3 有效電阻法 30
3-4 重要節點邊界搜尋法 31
3-5 最小電阻路徑搜尋法 34
3-6 周邊電阻搜尋法 38
第四章、實驗結果 43
4-1 實驗環境 43
4-2 實驗結果與比較 45
第五章、結論 62
參考文獻 63

參考文獻

[1] Z. Ye, D. Vasilyev, Z. Zhu, and J. R. Phillips, "Sparse implicit projection (SIP) for reduction of general many-terminal networks," in Proceedings of ACM/IEEE International Conference on Computer-Aided Design, pp. 736-743, November 2008
[2] A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 645-654, August. 1998.
[3] B. N. Sheehan, "Realizable reduction of RC networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1393-1407, August 2007.
[4] T. A. Davis, Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2), Society for Industrial and Applied Mathematics, Philadelphia, PA, 2006
[5] K. J. Kerns, and A. T. Yang, " Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 7, pp. 734-744, July 1997.
[6] P. Miettinen, M. Honkala, J. Roos, and M. Valtonena, " PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 3, pp. 374-387, March 2011.
[7] R. Ionutiu, J. Rommes, and W. H. A. Schilders, "SparseRC: Sparsity preserving model reduction for RC circuits with many terminals," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 12, pp. 1828-1841, December 2011.
[8] M. S. Lee, “Front-End Supply Current Waveform Models for Dynamic IR-Drop Analysis,” Ph.D.dissertation, Department of Electrical Engineering, National Central University, Taiwan, ROC, 2012.
[9] S. P. McCormick, “Modeling and simulation of VLSI interconnections with moments,” Ph.D. dissertation, Massachusetts Institute of Technology, 1989.
[10] A. J. van Genderen and N. P. van der Meijs, “Reduced RC models for IC interconnections with coupling capacitances,” in Proceedings of IEEE European Conference on Design Automation, pp. 132-136, March 1992.
[11] Y. Zhong, and M. D. F. Wong, "Fast algorithms for IR drop analysis in large power grid," in Proceedings of ACM/IEEE International Conference on Computer-Aided Design, pp. 351-357, November 2005.
[12] P. Feldmann, and F. Liu, "Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals," in Proceedings of ACM/IEEE International Conference on Computer-Aided Design, pp. 88-92, November 2004.
[13] R. W. Freund, "SPRIM: structure-preserving reduced-order interconnect macromodeling," in Proceedings of ACM/IEEE International Conference on Computer-Aided Design, pp. 80-87, November 2004.
[14] Joost Rommes, and W. H. A. Schilders, "Efficient Methods for Large Resistor Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 28-39, January 2010.
[15] C. W. Liu, and Y. W. Chang, "Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 693-704, April 2007.
[16] S. R. Nassif, and J. N. Kozhaya, “Fast power grid simulation,” in Proceedings of Design Automation Conference, pp. 156-161, 2000.
[17] M. Celik, L. Pileggi, and A. Odabasioglu, IC Interconnect Analysis, Boston: Kluwer Academic Publishers, 2002
[18] MathWorks. Reordering Algorithms [Online]. Available:
http://www.mathworks.com/help/matlab/reordering-algorithms.html
[19] ANSYS. (2012). Chip−Package−System (CPS) Co-design and Thermal Management of Electronics [Online]. Available:
http://resource.ansys.com/staticassets/ANSYS/staticassets/resourcelibrary/presentation/chip-package-system-design-2012-pres.pdf
[20] J. Zheng, “Chip-Package-Board Co-Design / Co-Verification Technology for DDR3 1.6G in Consumer Products,” Apache., ASP-DAC Designer’s Forum. January, 2011. [Online]. Available:
http://www.aspdac.com/aspdac2011/archive/pdf/5D-1.pdf
[21] PrimeRail User Guide: Dynamic Analysis X-2005.09, Synopsys, September 2005

指導教授

周景揚(Jing-Yang Jou)

審核日期

2016-8-23

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