1T1R憶阻器記憶體的 邊界電流識別和可靠性增強技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：123

、訪客IP：3.144.7.118

姓名

林姿穎(TZU-TING LIN) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

1T1R憶阻器記憶體的邊界電流識別和可靠性增強技術
(Boundary Current Identification and Reliability-Enhancement Techniques for 1T1R Memristor Memories)

相關論文

★ 應用於三元內容定址記憶體之低功率設計與測試技術	★ 用於隨機存取記憶體的接線驗證演算法
★ 用於降低系統晶片內測試資料之基礎矽智產	★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法
★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試	★ 用於系統晶片中單埠與多埠記憶體之自我修復技術
★ 用於修復嵌入式記憶體之基礎矽智產	★ 自我修復記憶體之備份分析評估與驗證平台
★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計	★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
★ 低功率與可自我修復之三元內容定址記憶體設計	★ 多核心系統晶片之診斷方法
★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產	★ 應用於貪睡靜態記憶體之有效診斷與修復技術
★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案	★ 應用於隨機存取記憶體之有效良率及可靠度提升技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

憶阻器被認為是用來替代未來非揮發性記憶體的一種非揮發性裝置。對於憶阻器記憶體而言，需要有參考電流來區分高阻抗和低阻抗。因此參考電流對於憶阻器的良率和可靠度有很大的衝擊，所以參考電流的設置是非常重要的。如果我們可以找到高阻抗跟低阻抗的邊界電流，我們就可以設置更佳的參考電流。因此，我們需要有可找到邊界電流的有效方法。

在這篇論文當中，我們提出一個測試方法去找到1T1R憶阻器記憶體的高阻抗跟低阻抗邊界電流。如此一來，使用者可以藉由邊界電流設置更好的參考電流。實驗結果顯示，如果使用我們提出的測試方法，我們可以減少10%的憶阻器被讀取錯誤。另一方面，高阻抗跟低阻抗的比值會隨者使用的時間越久而下降，為了解決這個問題，我們針對1T1R憶阻器記憶體提出一個線上監測和調校技術(OMT)。這種技術可以有效地延長記憶體的讀/寫週期。實驗結果顯示，OMT技術可以擴展憶阻器存儲器的壽命從10^5到10^6個存取周期。

摘要(英)

Abstract
Memristor is a resistive device which is considered as an alternative non-volatile device for future non-volatile memories. For a memristor memory, a reference current is needed for discriminating the high-resistance (ROFF ) state from the low-resistance (RON) state. The reference current has an impact on the yield and reliability of the memristor memory. If we can identify the boundary currents of ROFF and RON, a good reference current can be set. Therefore, effective methods for identifying the boundary currents of memristor memories are needed.
In this thesis, we propose a test method in associate with a current comparing circuit for finding the boundary currents of ROFF and RON states of 1T1R memristor memories. Therefore, the user can set a good reference current according to the boundary currents. Simulation results show that if the test method is used to identify the boundary currents, 10% memristor cells which may be read incorrectly due to process variation for ROFF/RON
=3 can be eliminated. On the other hand, the ROFF/RON resistance ratio will decrease with the increasing of the read/write cycles in use. This results in the reliability issue. To cope with this issue, we propose a online monitoring and tuning(OMT) technique for the 1T1R memristor memories. The OMT technique can effectively prolong the read/write cycles of the memristor memories. Simulation results show that if the OMT technique can extend the lifetime of the memristor memory from 105 to 106 access cycles.

關鍵字(中)

★ 憶阻器
★ 記憶體

關鍵字(英)

★ memristor
★ memory

論文目次

1.1 Memristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Memristor Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 1T1R Memristor Memristor . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Process Variation and Endurance . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Impact of Process Variation . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Read and Write Disturbance . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Boundary Current Identification Technique for Memristor Memory 10
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 The Method for Finding Boundary Currents . . . . . . . . . . . . . . . . . . 11
2.2.1 Proposed Test Methodology . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 The Test Flow for Finding the Boundary Currents . . . . . . . . . . . 12
2.3 Current Comparing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Current Comparing Circuit 1 . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Current Comparing Circuit 2 . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 Comparing Cells in the Current Comparing Circuit . . . . . . . . . . 18
2.3.4 Comparing Cells with Process Variation . . . . . . . . . . . . . . . . 30
2.4 Schematic of the Proposed Current Comparing Circuit . . . . . . . . . . . . 39
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3 An Online Monitoring and Tuning Method for 1T1R Memristor Memories
42
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 Online Monitoring and Tuning Method . . . . . . . . . . . . . . . . . . . . 44
3.2.1 Symmetric online Monitoring and Tuning Method . . . . . . . . . . 44
3.2.2 Skewed Online Monitoring and Tuning Method . . . . . . . . . . . . 44
3.2.3 Memristor Memory with Online Monitoring and Tuning Circuit . . . 45
3.3 Simulation and Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4 Conclusion 54

參考文獻

[1] D. Homouz, B. Mohammad, H. Elgabra, and I.Farahat, “Memristor: Modeling read
and write operations,” in ICM Proceeding, 2011, pp. 1–5.
[2] S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “TEAM: Threshold
adaptive memristor model,” IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 60, no. 1, pp. 211–221, Jan. 2013.
[3] L. Zheng, S. Shin, and S. M. S. Kang, “Modular structure of compact model for memristive
devices,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61,
no. 5, pp. 1390–1399, May 2014.
[4] R. S. Williams, “How we found the missing memristor,” IEEE Spectrum, vol. 45, no. 12,
pp. 28–35, Dec 2008.
[5] S. Hamdioui, H. Aziza, and G. C. Sirakoulis, “Memristor based memories: Technology,
design and test,” in Design Technology of Integrated Systems In Nanoscale Era, 2014,
pp. 1–7.
[6] Y. Ho, G. M. Huang, and P. Li, “Dynamical properties and design analysis for nonvolatile
memristor memories,” IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 58, no. 4, pp. 724–736, April 2011.
[7] M. D. Ventra, Y. V. Pershin, and L. O. Chua, “Circuit elements with memory: Memristors,
memcapacitors, and meminductors,” Proceedings of the IEEE, vol. 97, no. 10,
pp. 1717–1724, Oct. 2009.
[8] H. Manem, J. Rajendran, and G. S. Rose, “Design considerations for multilevel cmos
nano memristive memory,” ACM Jour. on Emerging Tech. in Computing System, vol. 8,
no. 1, pp. 6:16:22,, Feb 2012.
[9] D. R. S. D. B. Strukov, G. S. Snider and S. R.Williams, “The missing memristor found,”
in Nature Letters, 2008, pp. 80–83.
[10] N. Z. Haron, N. Arshad, and S. H. Herman, “Detecting resistive-opens in rram using
programmable dft scheme,” in Quality Electronic Design (ASQED), 2013 5th Asia
Symposium on, 2013, pp. 22–26.
[11] Y. Ho, G. M. Huang, and P. Li, “Nonvolatile memristor memory: Device characteristics
and design implications,” in IEEE/ACM International Conference on Computer-Aided
Design - Digest of Technical Papers, 2009, pp. 485–490.
[12] C. Xu, X. Dong, N. P. Jouppi, and Y. Xie, “Design implications of memristor-based
rram cross-point structures,” in 2011 Design, Automation Test in Europe, 2011, pp.
1–6.
[13] H. Mostafa and Y. Ismail, “Memristor-based memory: The sneak paths problem and
solutions,” Microelectronics Journal, vol. 44, no. 2, pp. 176183,, Feb 2013.
[14] S. Kannan, J. Rajendran, R. Karri, and O. Sinanoglu, “Sneak-path testing of crossbarbased
nonvolatile random access memories,” IEEE Transactions on Nanotechnology,
vol. 12, no. 3, pp. 413–426, May 2013.
[15] M. J. Lee, Y. Park, B. S. Kang, S. E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich,
J. H. Lee, S. J. Chung, Y. H. Kim, C. S. Lee, J. B. Park, I. G. Baek, and I. K. Yoo, “2-
stack 1d-1r cross-point structure with oxide diodes as switch elements for high density
resistance ram applications,” in 2007 IEEE International Electron Devices Meeting,
2007, pp. 771–774.
[16] S. Hamdioui, H. Aziza, and G. C. Sirakoulis, “Memristor based memories: Technology,
design and test,” in Design Technology of Integrated Systems In Nanoscale Era (DTIS),
2014 9th IEEE International Conference On, 2014, pp. 1–7.
[17] M. Zangeneh and A. Joshi, “Design and optimization of nonvolatile multibit 1T1R
resistive RAM,” IEEE Transactions on Very Large Scale Integration Systems, vol. 22,
no. 8, pp. 1815–1828, Aug 2014.
[18] H. Mostafa and Y. Ismail, “Process variation aware design of multi-valued spintronic
memristor-based memory arrays,” IEEE Transactions on Semiconductor Manufacturing,
vol. 29, no. 2, pp. 145–152, May 2016.
[19] D. Niu, Y. Chen, C. Xu, and Y. Xie, “Impact of process variations on emerging memristor,”
in Design Automation Conference, 2010, p. 877882.
[20] H. Liu, H. Lv, X. Xu, R. Liu, L. Li, Q. Liu, S. Long, Y.Wang, Z. Huo, and M. Liu, “Gate
induced resistive switching in 1T1R structure with improved uniformity and better data
retention,” in IEEE International Memory Workshop, 2014, pp. 1–2.
[21] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y.
Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M. J. Tsai,
“Highly scalable hafnium oxide memory with improvements of resistive distribution and
read disturb immunity,” in IEEE International Electron Devices Meeting, 2009, pp. 1–4.
[22] T. N. Kumar, H. A. F. Almurib, and F. Lombardi, “Operational fault detection and
monitoring of a memristor-based lut,” in 2015 Design, Automation Test in Europe
Conference Exhibition (DATE), 2015, pp. 429–434.
[23] S. Yu, X. Guan, and H. S. P. Wong, “On the switching parameter variation of metal oxide
rram -part ii: Model corroboration and device design strategy,” IEEE Transactions
on Electron Devices, vol. 59, no. 4, pp. 1183–1188, April 2012.
[24] B. Chen, Y. Lu, B. Gao, Y. H. Fu, F. F. Zhang, P. Huang, Y. S. Chen, L. F. Liu, X. Y.
Liu, J. F. Kang, Y. Y. Wang, Z. Fang, H. Y. Yu, X. Li, X. P. Wang, N. Singh, G. Q.
Lo, and D. L. Kwong, “Physical mechanisms of endurance degradation in tmo-rram,”
in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 12.3.1–12.3.4.
[25] S. N. Mozaffari, S. Tragoudas, and T. Haniotakis, “More efficient testing of metal-oxide
memristor-based memory,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. PP, no. 99, pp. 1–1, 2016.
[26] T. K. Chien, L. Y. Chiou, S. S. Sheu, J. C. Lin, C. C. Lee, T. K. Ku, M. J. Tsai, and C. I.
Wu, “Low-power mcu with embedded reram buffers as sensor hub for iot applications,”
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 2,
pp. 247–257, June 2016.
[27] S. Kvatinsky, K. Talisveyberg, D. Fliter, A. Kolodny, U. C. Weiser, and E. G. Friedman,
“Models of memristors for spice simulations,” in Electrical Electronics Engineers in
Israel (IEEEI), 2012 IEEE 27th Convention of, 2012, pp. 1–5.
[28] T. Na, J. P. Kim, S. H. Kang, and S. O. Jung, “Multiple-cell reference scheme for narrow
reference resistance distribution in deep submicrometer stt-ram,” IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 24, no. 9, pp. 2993–2997, Sept 2016.
[29] A. Benoist, S. Blonkowski, S. Jeannot, S. Denorme, J. Damiens, J. Berger, P. Candelier,
E. Vianello, H. Grampeix, J. F. Nodin, E. Jalaguier, L. Perniola, and B. Allard, “28nm
advanced cmos resistive ram solution as embedded non-volatile memory,” in 2014 IEEE
International Reliability Physics Symposium, 2014, pp. 2E.6.1–2E.6.5.
[30] Y. Y. Chen, R. Degraeve, S. Clima, B. Govoreanu, L. Goux, A. Fantini, G. S. Kar,
G. Pourtois, G. Groeseneken, D. J. Wouters, and M. Jurczak, “Understanding of the
endurance failure in scaled hfo2-based 1t1r rram through vacancy mobility degradation,”
in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, pp. 20.3.1–20.3.4.
[31] P. Pouyan, E. Amat, and A. Rubio, “Statistical lifetime analysis of memristive crossbar
matrix,” in Design Technology of Integrated Systems in Nanoscale Era, 2015, pp. 1–6.

指導教授

李進福(Jin-Fu Li)

審核日期

2016-12-22

推文