以戴爾他模型為基礎的漸進式電路壽命分析技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：23

、訪客IP：18.227.21.225

姓名

何思蓉(Si-Rong He) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以戴爾他模型為基礎的漸進式電路壽命分析技術
(An incremental simulation technique based on delta model for lifetime yield analysis)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路	★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究	★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬	★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器	★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究	★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究	★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計	★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

當積體電路製程尺寸越來越小，元件中因老化(aging)現象所導致的參數改變對良率的影響也越來越嚴重，常常使得電路效能(performance)不如預期，甚至會讓電路在一段時間之後就無法正常工作，因此設計電路時，更需要將電路老化的分析加入標準的流程之中，提升產品出廠後的可靠度。然而在傳統的老化分析中，需在模擬時間與準確度之間做取捨，若以模擬時間為考量，通常會直接以出廠時的參數來推估老化後的參數，然而在老化的過程中，電路的參數會跟著不停的變動，若是沒有更新這些參數，將使得老化分析結果不夠準確；若以準確度為考量，在分析過程中不斷更新電路參數，雖然可以得到準確的分析結果，卻需要非常多次的模擬才能完成，而花費相當多的時間。
為了改善現今老化分析的準確度以及模擬速度。本論文提出一個以戴爾他模型為基礎的漸進式電路壽命分析技術，最大的特點在於老化分析時，使用漸進式(incremental)的方式來更新老化所導致的參數改變，以保持電路老化分析的精準度，另外再加上戴爾他模擬(delta simulation)的方式來加快模擬的速度，以達到最佳的效能。由實驗結果觀察可知，本論文所提出的方法確實有效提升了分析速度，也能同時保持老化分析的精準度，是ㄧ個兼顧效能與準確度的好方法。

摘要(英)

With the advance of VLSI technology, the parameter shift due to device aging has increasingly impacts on circuit yield. The aging effects may degrade circuit performance and cause circuit failure after a period of time. As a result, aging analysis is necessary in standard design flow to improve product reliability. Previous works of aging analysis have to find a trade-off between accuracy and simulation time. In order to reduce the simulation time, most of the previous works estimate the degraded device parameters based on the fresh design. However, the device parameters keep change during the aging process. If those parameters are not updated during the aging analysis, some errors will exist in the analysis results. In order to obtain accurate results, some analysis approaches try to continuously update the device parameters in the analysis procedure. Although the accuracy of estimation results is improved significantly, a lot of simulation time is required due to the huge number of simulations.
In order to improve the accuracy and simulation speed of the aging analysis, this thesis proposes an incremental simulation technique based on delta model. This approach adopts incrementally updated device parameters during aging analysis to keep high accuracy. Furthermore, delta simulation concept as well as the dynamic aging sampling are adopted to reduce the simulation time. As demonstrated in the experimental results, the proposed approach is an effective way to obtain high speed-up and keep estimation accuracy.

關鍵字(中)

★ 壽命良率分析
★ 電路老化
★ 戴爾他模擬
★ 漸進式
★ 蒙地卡羅統計

關鍵字(英)

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章、緒論 1
1.1 研究動機 1
1.2 相關研究 5
1.2.1 Berkeley Reliability Tool (BERT) 5
1.2.2 Cadence RelXpert 6
1.2.3 ELDO 7
1.2.4 依比率預測老化參數之方法 8
1.3 論文結構 10
第二章、背景知識 11
2.1 電路老化的成因 11
2.1.1 熱載子注入 12
2.1.2 絕緣崩潰 14
2.1.3 電子遷移 14
2.1.4 負偏壓溫度不穩定性 15
2.2 統計分析方法 16
2.2.1 降低時間點所需的樣本數量 17
2.2.2 壽命良率分析之概念 19
2.2.3 所使用的電路老化模型 20
第三章、漸進式老化分析方法 22
3.1 戴爾他電路 22
3.1.1 戴爾他電路概念 22
3.1.2 戴爾他電路之電路參數 25
3.2 用於電路老化的漸進式分析方法 29
3.2.1 電路老化的漸進式分析之概念 29
3.2.2 動態取樣分析之概念 32
3.2.3 漸進式電路老化分析之流程圖 33
第四章、實驗結果 35
4.1 二階NMOS放大器 35
4.1.1 漸進式分析方法 36
4.1.2 漸進式分析加上戴爾他模擬 37
4.1.3 蒙地卡羅統計分析 38
4.2 Voltage Bandgap Reference電路 41
4.2.1 漸進式分析方法 41
4.2.2 漸進式分析加上戴爾他模擬 43
4.2.3 蒙地卡羅統計分析 44
第五章、結論 47
參考文獻 48

參考文獻

[1] G. E. Moore, “Cramming More Components Onto Integrated Circuits,” Proceedings of the IEEE, Jan 1998.
[2] Y.-L. Chen, W. Wu, C.-N. J. Liu, and L. He, “Incremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits,” Asia and South Pacific Design Automation Conference, Jan. 2015.
[3] R.T. Hu, et. al., “Berkeley Reliability Tools-BERT”, IEEE Tran. On Computer Aided Design of Integrated Circuits and Systems, vol. 12, no. 10,1993.
[4] Virtuoso relxpert reliability simulator user guide, Product version 7.0.1,June 2008.
[5] Cadence White paper. Reliability Simulation in Integrated Circuit Design. http://www.cadence.com/
[6] Medhat Karam, Wael Fikry, Hani Ragai. Implementation of Hot-Carrier Reliability Simulation in Eldo. Mentor Graphics Deep Submicron Technical Publication, Sep. 2000.
[7] G. Gielen, P. De Wit, E. Maricau, J. Loeckx, J. Mart’?n-Mart’?nez, B. Kaczer, G. Groeseneken, “Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies,” Design Automation and Test in Europe, pp. 1322-1327, 2008.
[8] J. E. Chung, K. N. Quader, C. G. Sodini, P. K. Ko, and C. Hu, “The Effects of Hot-Electron Degradation on Analog MOSFET Performance,” Int’l Electron Device Meeting, pp. 553-557, 1990.
[9] X. Pan, H. Graeb, “Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations,” Advances in Analog Circuits, Feb. 2011.
[10] http://eshare.stut.edu.tw/EshareFile/2010_5/2010_5_97e83edf.ppt.
[11] A. Singhee and R. Rutenbar, “From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis,” Int’l Symp. on Quality Electronic Design, Mar. 2007.
[12] J. Jaffari and M. Anis, “On Efficient LHS-Based Yield Analysis of Analog Circuits,” IEEE Trans. on Computer-Aided Design, vol. 30, no. 1, pp. 159–163, Jan. 2011.
[13] M. McKay, R. Beckman, and W. Conover, “A Comparison of Three Methods for Selecting Values of Input Variables in the Analysis of Output from a Computer Code,” Technometrics, pp. 239–245, 1979.
[14] S. Vrudhula, J. Wang, and P. Ghanta, “Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations,” IEEE Trans. on Computer-Aided Design, vol. 25, no. 10, pp. 2001–2011, 2006.
[15] F. Gong, S. Basir-Kazeruni, L. He, and H. Yu, “Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits,” IEEE Trans. on Computer-Aided Design, vol. 32, no. 1, pp. 24–33, Jan. 2013.
[16] X. Li, J. Le, P. Gopalakrishnan, and L. Pileggi, “Asymptotic Probability Extraction for Non-normal Performance Distributions,” IEEE Trans. on Computer-Aided Design, vol. 26, no. 1, pp. 16–37, 2007.
[17] R. Krishnan, W. Wu, F. Gong, and L. He, “Stochastic Behavioral Modeling of Analog/Mixed-Signal Circuits by Maximizing Entropy,” Int’l Symp. on Quality Electronic Design, Mar. 2013.
[18] W. Wu, Y. Shan, X. Chen, Y. Wang, and H. Yang, “FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations,” in Reconfigurable Computing: Architectures, Tools and Applications. Springer, 2011.
[19] W. Wu, F. Gong, R. Krishnan, L. He, and H. Yu, “Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms,” IEEE Design&Test of Computers, vol. 30, no. 1, pp. 26–35, Feb 2013.
[20] X. Chen, W. Wu, Y. Wang, H. Yu, and H. Yang, “An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 10, pp. 702 –706, Oct. 2011.
[21] T-Y. Zhou, H. Liu, D. Zhou, and T. Tarim, “A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification,” IEEE Trans. on Computer-Aided Design, vol. 30, no. 2, pp. 308–313, Feb. 2011.
[22] “HSPICE User Guide”, Version A-2008.03, Synopsys, Mar. 2008.
[23] W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan and Y. Cao,“Compact modeling and simulation of circuit relaibility for 65nm CMOS technology”, IEEE Transactions on Device and Materials Reliability, vol.7, no. 4, pp. 509-517, 2007.
[24] X. Pan and H. Graeb, “Degradation-aware analog design flow for lifetime yield analysis and optimization,” in Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on, Dec. 2009, pp. 667–670.
[25] E. Maricau and G. Gielen, “Efficient Reliability Simulation of Analog ICs Including Variability and Time-varying Stress,” in Design, Automation and Test in Europe (DATE), 2009
[26] Electrical breakdown – Wikipedia. https://en.wikipedia.org/wiki/
Electrical_breakdown
[27] Electromigration – Wikipedia. https://en.wikipedia.org/wiki/
Electromigration
[28] E. H. Ma and C. M. Li, “DC analysis for flexible TFT circuits considering process variation, aging, and bending effects,” M.S. thesis, Dep. Graduate Inst. Elect. Eng., National Taiwan Univ., Taipei, Taiwan, Sep. 2010.
[29] H. I. Lee, C. Y. Han and C. M. Li, “A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse” IEEE Trans. on Computer-Aided Design, vol. 35, no. 7, pp. 1130-1137, Jul. 2016

指導教授

劉建男

審核日期

2017-1-20

推文