博碩士論文 88225012 詳細資訊




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姓名 許嘉仁(Jian-Run Hsu)  查詢紙本館藏   畢業系所 統計研究所
論文名稱 穩健且具高抗損率的迴歸估計
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摘要(中) 在元件之直流特性方面,1.0 mm ’ 50 mm之元件,其汲極飽和電流為215 mA/mm,夾止電壓為 -1.9 V;元件最大轉移電導gm為152 mS/mm。在高頻特性方面,元件偏壓在VDS = 2.0 V,VGS = 0 V時,量測求得電流增益截止頻率(ft)為8 GHz,功率增益截止頻率(fmax)為25 GHz。
另外,為了改善元件之崩潰特性與鈍化層的處理,針對表面植入氧之元件進行研究。經由實驗證明,氧的植入確實能有效改善元件之崩潰特性,更可以省略表面鈍化層的製程,但只對於元件之直流和高頻特性帶來了少許的傷害。
關鍵字(中) ★ 離子佈植
★ 砷化鎵金屬半導體場效電晶體
關鍵字(英) ★ Ion-implantation
★ MESFET
論文目次 目 錄
第一章 緒論…………………………………………………………1
§1.1 無線通訊的發展………………………………………………1
§1.2 論文架構………………………………………………………4
第二章 砷化鎵金屬半導體場效電晶體…………………………5
§2.1 砷化鎵場效電晶體……………………………………………5
§2.2 離子佈植砷化鎵場效電晶體…………………………………8
§2.2.1 離子佈植法………………………………………………8
§2.3.2 P型埋藏層………………………………………………13
第三章 離子佈植後之最佳活化溫度與時間……………………15
§3.1 活化的概念和應用…………………………………………15
§3.2 霍耳效應量測………………………………………………18
§3.3 電容-電壓特性量測…………………………………………23
第四章 離子佈植砷化鎵場效電晶體之製程……………………27
§4.1 離子佈植……………………………………………………29
§4.2 清洗晶片……………………………………………………30
§4.3 快速加熱處理………………………………………………30
§4.4 元件的隔離…………………………………………………31
§4.5 歐姆接觸電極製作…………………………………………32
§4.5.1 歐姆接觸之最佳退火溫度與時間………………………32
§4.5.2 歐姆接觸電極製程………………………………………35
§4.6 閘極掘入和閘極電極製作…………………………………36
§4.6.1 閘極掘入…………………………………………………37
§4.6.2 閘極電極製程……………………………………………38
§4.7 覆蓋鈍化層與製作介層洞…………………………………40
§4.8 金屬連線的製作……………………………………………41
第五章 離子佈植砷化鎵場效電晶體之特性與討論……………43
§5.1 元件的直流特性與討論……………………………………43
§5.2 元件的高頻特性與討論……………………………………48
第六章 特殊氧植入離子佈植砷化鎵場效電晶體之研究……54
§6.1 元件製成上的修正…………………………………………54
§6.2 元件特性上的改變…………………………………………55
§6.2.1 元件直流特性上的改變…………………………………55
§6.2.2 元件高頻特性上的改變…………………………………59
第七章 結論………………………………………………………62
參考文獻……………………………………………………………64
參考文獻 [1] C. A. Mead:"Schottky Barrier Gate Field Effect Transistor," Proc. IEEE, 54, pp.307-308(1966)
[2] K. Drangeid, R. Sommerhalcler and W. Walter: "High-speed gallium arsenide Schottky-barrier field effect transistors," Electron, Lett., Vot. 6, pp.228-229, April 1970
[3] For a discussion on ion implantation in silicon, see, for example. T. E. Seidel, "Ion Implantation," in S. M. Sze, Ed., VLSI Technology, McGraw-Hill, New York, 1983.
[4] I. Brodie and J. J. Muray, The Physics of Microfabrication, Plenum, New York, 1982.
[5] S. M. Sze, "Semiconductor Devices: Physics and Technology," Chap. 10, John Wiley & Sons, 1985.
[6] M. T. Robinson, and O. S. Oen, Applied Physics Letter, vil. 2, pp. 30, 1963.
[7] R. A. Moline, J. Applied Physics, vol. 42, pp. 3553, 1973.
[8] R. G. Wilson, J. Applied Physics, vol.52, pp. 3985, 1985.
[9] K. Yamazaki, N. Kato, and M. Hirayama, "Below 10ps/Gate Operation with Buried P-Layer SAINT FETs," Electronics Letters, Vol. 20, Nos. 25/26, p.1029, 1984.
[10] K. Yamazaki, N. Kato, and M. Hirayama, "Buried P-Layer for Very High Speed GaAs LSI’’s with Submicrometer Gate Length," IEEE Transactions on Electron Device, Vol. ED-32, No. 11, p.2430, 1985.
[11] K. L. Tan, H. K. Chung, and C. H. Chen, "Improvement in Threshold Implanted P Layer," IEEE Electron Device Letters, Vol. EDL-8, No. 9, p.440, 1987.
[12] Y. Umemoto, S. Takahashi, N. Matsunaga, and M. Nakamura, "GaAs MESFETs with A Buried P-Layer for Large Scale Integration," Electronics Letters, Vol. 20, No. 2, p.98, 1984.
[13] K. L. Tan, H. K. Chung, B. L. Grung, and S. M. Shin, "A Submicron Self-Align Gate MESFET Technology for Low Power Subnanosecond Static RAM Fabrication," IEEE GaAs IC Symposium, p.121, 1987.
[14] N. Matsunaga, M. Miyazaki, Y. Umemoto, J. Shigeta, H. Tanaka, and H. Yanazawa, "Gallium Arsenide MESFET Technologies with 0.7mm Gate-Length for 4kb 1ns Static RAM," IEEE GaAs IC Symposium, p.129, 1987.
[15] P. C. Canfield and L. Forbes, "Buried Channel GaAs MESFET’’s with Frequency-Independent Output Conductance," IEEE Electron Device Letters, Vol. EDL-8, p.88, 1987.
[16] J. M. Pate, et al., Surface Modification and Alloying, Plenum, 1983, p.133.
[17] Y. Shioya and M. Maeda, J. of Applied Physics, Vol. 60, 1986, p.327.
[18] D. Pramanik, et al., Semiconductor International, May 1985.
[19] S. Prussin, et al., J. Applied Physics, Vol. 57, 1985, p.180.
[20] S. Wolf, Silicon Processing for the VLSI Era, Vol. 1, Ch. 9, Lattice Press, 1986.
[21] S. R. Wilson, Solid State Technology, June 1985, p.185.
[22] S. J. Lee and C. R. Crowell, "Parasitic source and drain resistance in high-electron-mobility transistor," Solid-state Electron, Vol. 28, p.659-668, 1985.
[23] Dieter K. Schroder, Semiconductor Material and Device Characterization, Wiley-Interscience, 1990.
[24] N. Braslau, "Alloyed Ohmic Contact to GaAs," Journal of Vaccum Science & Technology B, Vol. 19, No. 3, 1981.
[25] M. Heiblum, M. I. Nathan, and C. A. Chang, "Characteristics of AuGeNi Ohmic Contact to GaAs," Solid State Electronics, Vol. 11, No. 6, p.2505, 1993.
[26] R. T. Tung, "Electron Transport of Inhomongeneous Schottky Barrier," Appl. Phys. Lett. 58, 2821-2823, 1991.
[27] C. R. Crowell, J. C. Sarace and S. M. Sze, "Tungsten-Semiconductor Schottky-Barrier Diodes," Trans. Met Soc. AIME, 233, 478, 1965.
[28] G. Gonzalez, "Microwave Transistor Amplifier Analysis and Design, " Prentice-hell, 1984.
[29] B. E. Maile, "Fabrication Limits of Nanometer T and G Gates: Theory and Experiment," Journal Vaccum Science and Technology B, Vol. 11, No. 6, p.2502, 1993.
指導教授 鄭松壽(Sung-Shou Cheng) 審核日期 2002-1-15
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