應用於雙倍資料率同步動態隨機存取記憶體之全數位式延遲鎖定迴路

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邱郁廷(Yu-Ting Chiu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於雙倍資料率同步動態隨機存取記憶體之全數位式延遲鎖定迴路
(An All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application)

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摘要(中)

隨著消費性電子的蓬勃發展，中央處理器需操作在更高速度以滿足更高品質的需求，而雙倍資料率同步動態隨機存取記憶體作為中央處理器的重要周邊亦無法倖免。然而，越高的操作速度代表著越大百分比的時脈扭曲，因此，時脈同步是必須的。在傳統延遲鎖定迴路電路設計當中，操作速度瓶頸往往受限於電路本身之固有延遲，若是高於操作頻率上限或低於操作頻率下限，則電路將發生阻塞鎖定或諧波鎖定。為了避免阻塞鎖定，許多延遲鎖定迴路被設定為單方向追鎖，而諧波鎖定在單一相位輸出之延遲鎖定迴路當中可被忽略。然而，應用於雙倍資料率同步動態隨機存取記憶體之延遲鎖定迴路除了同相位之外，電路需額外提供正交相位，若發生諧波鎖定，則會造成相位錯誤或遺失，進而導致誤動作。
因此，本論文提出一應用於雙倍資料率同步動態隨機存取記憶體之全數位式延遲鎖定迴路，透過所提出之諧波鎖定偵測與自我校正技術，本論文晶片可實現100 MHz至2.7 GHz之操作範圍，其成果不僅適用於第四代產品，也能向下相容於第一代至第三代之產品。此外，本論文晶片使用TSMC 90 nm CMOS 1P9M (TN90GUTM)製程來實現，電路操作電壓為1 V。根據量測結果，本論文晶片輸出時脈之週期至週期抖動峰對峰值小於0.019 UI、均方根值小於0.003 UI，而週期抖動峰對峰值小於0.014 UI、均方根值小於0.003 UI，電路功率消耗小於49.8 mW，整體晶片面積為0.903 mm^2，核心電路面積為0.089 mm^2。

摘要(英)

With the flourishing of consumer electronics, Central Processing Unit (CPU) has to be operated in higher frequency to meet the higher quality requirement. The Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) as the important peripheral of CPU cannot be spared, either. However, the higher operating frequency indicates the larger percentage of clock skew. Therefore, the clock synchronization is necessary. In a normal Delay-Locked Loop (DLL) design, the bottleneck of operating frequency is always limited by the inherent delay of the circuits. If the operating frequency is higher than the upper limit or lower than the lower limit, the stuck lock or harmonic lock will be happened. To avoid the stuck lock, many DLLs were designed as tracking for only one direction. As for the harmonic lock, it can be ignored in the DLLs which only output in phase signal. However, the phase requirement of DLL applied in DDR SDRAM is not only in phase signal, but quadrature phase signal. If the harmonic lock occurs in the DLL applied in DDR SDRAM, the quadrature phase signal will be fault or miss, which induce the mistakes.
To avoid the quadrature phase error causing by the harmonic lock, a novel harmonic lock detection and auto calibration technique is propose in this thesis. The chip was fabricated using TSMC 90 nm CMOS 1P9M (TN90GUTM) process with a 1-V supply voltage. The whole chip area and core area are 0.903 mm^2 and 0.089 mm^2, respectively. According to the measurement results, the operating frequency range of chip is from 100 MHz to 2.7 GHz with the power consumption less than 49.8 mW. The peak-to-peak and room-mean-square (RMS) cycle-to-cycle jitter are less than 0.019 UI and 0.003 UI, respectively. The peak-to-peak and RMS period jitter are less than 0.014 UI and 0.003 UI, respectively. These achievements make the chip suit for not only 4th DDR SDRAM, but from 1st to 3rd DDR SDRAM.

關鍵字(中)

★ 延遲鎖定迴路
★ 雙倍資料率同步動態隨機存取記憶體

關鍵字(英)

★ Delay-Locked Loop
★ Double Data Rate Synchronous Dynamic Random Access Memory

論文目次

摘要 i
Abstract iii
誌謝 v
目錄 vii
圖目錄 xi
表目錄 xix
第1章緒論 1
1.1 研究背景與動機 1
1.2 論文架構 3
第2章時脈同步電路與責任週期校正電路簡介 5
2.1 時脈同步電路 5
2.1.1 閉迴路時脈同步電路[2] 6
2.1.2 開迴路時脈同步電路[3] 7
2.2 責任週期校正電路 8
2.2.1 閉迴路責任週期校正電路[4] 8
2.2.2 開迴路責任週期校正電路[5] 9
第3章諧波鎖定偵測與自我校正技術 11
3.1 操作範圍與錯誤鎖定 11
3.2 諧波鎖定分析 12
3.3 諧波鎖定偵測與自我校正技術 15
第4章應用於雙倍資料率同步動態隨機存取記憶體之全數位式延遲鎖定迴路 19
4.1 系統架構與操作原理 19
4.1.1 系統架構 20
4.1.2 操作原理 21
4.2 子電路與設計考量 22
4.2.1 偵測電路 22
4.2.1.1 時間至數位轉換器 22
4.2.1.1.1 自我校正邊緣偵測器 24
4.2.1.1.2 可重複使用量測延遲元件 26
4.2.1.2 相位比較器 27
4.2.2 控制電路 28
4.2.2.1 時序控制器 29
4.2.2.2 粗調控制器 30
4.2.2.3 細調控制器 31
4.2.3 延遲電路 32
4.2.3.1 相位分佈器 32
4.2.3.2 粗調延遲線 33
4.2.3.3 細調延遲線 34
4.2.3.4 邊緣合成器 35
第5章實驗結果 37
5.1 晶片佈局與模擬結果 37
5.1.1 晶片佈局 37
5.1.2 模擬結果 38
5.2 量測考量與量測結果 42
5.2.1 量測考量 42
5.2.2 量測結果 45
第6章結論與未來展望 85
6.1 結論 85
6.2 未來展望 85
參考文獻 87
出版清單 89
研討會論文 89

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2017-7-19

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