濾波器組多載波系統之 接收端等化器設計與實現

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姓名

郭淑娜(Shu-Na Guo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

濾波器組多載波系統之接收端等化器設計與實現
(Equalizer Design and Implementation for Filter Bank Multicarrier System)

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摘要(中)

正交分頻多工器(Orthogonal Frequency Division Multiplexing, OFDM)傳輸技術利用子載波的正交特性及循環字首來消除符元間干擾及載波間干擾，而濾波器組多載波(Filter Bank Multicarrier, FBMC)傳輸系統使用偏移正交振幅調變(Offset Quadrature Amplitude Modulation, OQAM) 以及有良好阻帶衰減的濾波器維持相鄰子載波之間的正交特性，將干擾抑制在相鄰子載波間，並避免循環捲積混疊(circular convolution aliasing) ，因此不使用循環字首也可以消除符元間的干擾，進而也提高了頻寬使用率。
本論文針對在濾波器組多載波 (Filter Bank Multicarrier, FBMC)系統下的接收端，如何消除符元間干擾與子載波間干擾做分析。並且在WIMAX規格下使用前導符元(Preamble)進行通道估測(Channel Estimation)，再使用單一載波頻域等化器對通道效應進行資料回復的補償。等化器的選擇有三種；1.有限脈衝響應單一載波等化器， 2.最小均方根頻域等化器， 3.決策回授等化器。首先，會進行等化器的模擬與比較，然後因為決策反饋等化器能夠比其他等化器以更低的訊雜比通過10-2誤碼率的界線，因此選擇使用決策反饋等化器。電路部分使用Verilog HDL描述，並使用TSMC-90nm製程來實現所設計之電路，最後FPGA驗證其電路設計。

摘要(英)

Orthogonal frequency division multiplexing (OFDM) utilizes the quadrature characteristics of the subcarriers and the cyclic prefix to eliminate inter-symbol and inter-carrier interference. Filter bank Multicarrier (FBMC) uses offset quadrature amplitude modulation (OQAM) to maintain the orthogonality between adjacent subcarriers and a filter with good stopband attenuation to avoid the circular convolution aliasing. So the FBMC didn’t need the cyclic prefixes can also eliminate symbols between the interference, leading to higher bandwidth efficiency.
In this paper, we analyze how to eliminate the inter-symbol interference and inter-carrier interference in the receiver of the FBMC. Channel estimation is performed using the preamble under the WIMAX specification, and the channel effect is compensated using a single carrier frequency domain equalizer. Equalizer has three options: 1. Finite impulse response equalizer. 2. Minimum mean square frequency domain equalizer. 3. Decision feedback equalizer. We would compare those equalizers based on simulation results. The decision feedback equalizer employed since it is able to achieve the 10-2 bit error rate threshold at SNR that is lower than other equalizers. Decision feedback equalizer is descripted with Verilog HDL, and used FPGA to verify its circuit design.

關鍵字(中)

★ 濾波器組
★ 濾波器組多載波
★ 等化器

關鍵字(英)

★ FBMC
★ equalizer

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文架構 2
第二章濾波器組多載波介紹 3
2.1 正交分頻多工 3
2.1.1 循環字首 4
2.2 濾波器組多載波傳輸多工器介紹 5
2.2.1 濾波器組架構 7
2.2.2 偏移正交振幅調變 (OQAM) 10
第三章濾波器組多載波架構 12
3.1 原型濾波器 12
3.2濾波器組多載波時間頻率響應 14
3.2.1載波間干擾分析 16
3.2.1符元間干擾分析 19
第四章通道估測及等化 23
4-1通道估測 23
4-1-1干擾近似法 23
4-2有限脈衝響應濾波器的等化器 26
4-2-1 複數型有限脈衝響應濾波器 27
4-2-2 振幅相位單一載波等化器(Amplitude-Phase SubCarrier Equalizer, AP-SCE) 29
4-3 最小方均根(LMS)頻域等化器 31
4-3-1最小方均根演算法(Least Mean Square ,LMS) 31
4-3-2最小方均根單一載波頻域等化器 33
4-3-3決策回授等化器 35
第五章模擬結果與電路 40
5-1模擬環境 40
5-2模擬結果 41
5-3電路設計 45
5-4模擬與驗證結果 47
5-4-1定點數分析 47
5-4-2模擬結果驗證 48
5-4-3可程式化邏輯陣列驗證 49
第六章結論與未來展望 51
參考文獻 52

參考文獻

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2017-7-24

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