具無限脈衝響應及離散時間技術之5 Gb/s自適應決策回授等化器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：29

、訪客IP：3.23.101.62

姓名

劉哲維(Che-Wei Liu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具無限脈衝響應及離散時間技術之5 Gb/s自適應決策回授等化器
(A 5 Gb/s Adaptive Infinite-Impulse-Response Decision-Feedback Equalizer with Infinite-Impulse-Response DFE and Discrete-Time DFE Techniques)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著資料的傳輸頻寬不斷上升，而晶片與晶片間之通道頻寬並未隨之上升，資料將無法維持良好之訊號完整度，因此等化器被廣泛應用於接收端以補償資料經過通道產生的衰減，本論文參考USB3.0之規格實現具自無限脈衝響應及離散時間技術之5 Gb/s決策回授等化器電路。
由於通道之頻率響應特性為隨著資料傳輸速率上升，通道衰減量隨之線性增加，因此高速串列傳輸系統所面臨到的之通道衰減量變得不容小覷。對此較大之通道衰減量，若完全採用離散時間決策回授等化器，將造成過大之功率消耗。反之，若單純使用無限脈衝響應決策回授等化器，所面臨到的問題為回授訊號易受到製程及溫度變異而使得等化器產生過補償及欠補償的情況。因此本論文提出同時調整離散時間及無限脈衝響應決策回授等化器之方法，於第一個後游標之位置，藉由改變兩者所佔之權重，得到一個眼圖之最佳解，此方法可使無限脈衝響應決策回授等化器於製程及溫度變異下之眼寬得到最佳解。本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS製程來實現，電路操作電壓為1 V，輸入資料為5 Gbps，輸入時脈為5 GHz，在通道衰減量24 dB時，等化後資料的峰對峰值抖動量為45.78 ps，方均根抖動量為8.60 ps;在通道衰減量14 dB時，等化後資料的峰對峰值抖動量為30.22 ps，方均根抖動量為6.05 ps;在通道衰減量7 dB時，等化後資料的峰對峰值抖動量為24 ps，方均根抖動量為4.50 ps。在通道衰減24 dB下之整體功率消耗為9.8 mW，其中決策回授等化器電路之功率消耗為5.4 mW，自適應機制電路之功率消耗為4.4 mW。晶片面積為0.868 mm2，核心電路面積為0.037 mm2。

摘要(英)

As the data rate increasing, the signal integrity of high speed data transmission is worse since the limiting bandwidth of channel. Therefore, receivers generally adopt an equalizer to compensate for the signal attenuation caused by the channel. This study presents a 5 Gb/s adaptive infinite-impulse-response decision-feedback equalizer with infinite-impulse-response decision-feedback equalizer (IIR-DFE) and discrete-time decision-feedback equalizer (DT-DFE) Techniques, and takes USB 3.0 specification as reference material.
As the data rate increases, the channel loss increase linearly. Therefore, the channel loss should not be underestimated in the high speed serial link system. The power consumption becomes prohibitive if the equalizer fully adopts the DT-DFE technique for this larger channel loss. On the contrary, the feedback signal is easily affected by the process and temperature variations which cause the over compensation and under compensation if the equalizer fully adopts the IIR-DFE technique. In this thesis, the DT-DFE and the IIR-DFE are simultaneously controlled. This method can make the IIR-DFE get the best eye width under the process and temperature variation, by determining the both weights of two mechanisms to get the widest eye width at the first-post cursor position. This test chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process with 1 V supply voltage. The data rate is 5 Gbps and the DFE is operating at 5 GHz. When channel loss is 24 dB, the peak-to-peak jitter of equalized data is 45.78 ps, the root mean square (RMS) jitter of equalized data is 8.60 ps. When channel loss is 14 dB, the peak-to-peak jitter of equalized data is 30.22 ps, the RMS jitter of equalized data is 6.05 ps. When channel loss is 7 dB, the peak-to-peak jitter of equalized data is 24 ps, the RMS jitter of equalized data is 4.50 ps. The total power consumption of this work is 9.8 mW under 24 dB channel loss, and the power consumption of DFE and adaptive mechanism are 5.4 mW and 4.4 mW, respectively. The chip area is 0.868 mm2 and the core area is 0.037 mm2.

關鍵字(中)

★ 等化器
★ 決策回授等化器
★ 自適應

關鍵字(英)

★ equalizer
★ Decision-Feedback Equalizer
★ adaptive

論文目次

目錄
摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 vii
表目錄 xii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整性 5
2.1 基本觀念 5
2.1.1 隨機二位元資料特性 5
2.1.2 資料編排型式 6
2.1.3 傳輸線理論 7
2.1.4 單一位元脈衝響應與等化器之關係 12
2.2 眼圖分析 14
2.3 誤碼率 15
第3章決策回授等化器之背景簡介 19
3.1 決策回授等化器電路簡介 19
3.1.1 等化器電路的種類 19
3.1.2 自適應機制 23
3.2 傳統無限脈衝響應決策回授等化器電路 27
3.2.1 二階無限脈衝響應決策回授等化器 27
3.2.2 一階無限脈衝響應決策回授等化器與一階離散時間等化器 28
3.3 比較與討論 29
第4章自適應無限脈衝響應決策回授等化器電路設計與實現 31
4.1 電路架構 31
4.2 操作說明 33
4.2.1 離散時間決策回授等化器之單一位元脈衝響應示意圖 33
4.2.2 無限脈衝響應決策回授等化器之單一位元脈衝響應示意圖 34
4.2.3 同時調整機制之單一位元脈衝響應最佳解示意圖 36
4.3 行為模擬 38
4.4 子電路介紹 41
4.4.1 電流模式加法器電路 41
4.4.2 最小均方誤差自適應機制 44
4.5 模擬結果 46
4.5.1 通道模型 47
4.5.2 操作在5 GHz之決策回授等化器模擬 49
4.5.3 結果整理 70
第5章晶片佈局與量測 75
5.1 電路佈局 75
5.1.1 晶片封裝 76
5.1.2 佈局規劃與電源規劃 78
5.2 量測考量 79
5.2.1 量測環境 79
5.2.2 高頻輸出緩衝器 80
5.2.3 高頻資料輸入端 82
5.2.4 高頻時脈輸入端 82
5.2.5 M8048A ISI通道 83
5.3 晶片與印刷電路板照相 85
5.4 量測結果 86
5.4.1 具自適應之決策回授等化器電路量測 86
5.4.2 不同時脈與資料相對位置之量測結果 99
5.4.3 不同操作頻率下所能容忍之最大通道衰減量 101
5.5 分析與討論 106
5.6 規格比較表 107
第6章結論 109
6.1 結論 109
6.2 未來研究方向 110
參考文獻 111

參考文獻

參考文獻
[1] PCI Express® Base Specification, Revision 2.1, PCI-SIG, 2010.
[2] Serial ATA International Organization, Serial ATA Revision 3.0, SATA-IO, 2009.
[3] Universal Serial Bus Specification, Revision 3.1, USB-IO, 2013
[4] 孫世洋, “以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[5] B. Razavi, Design of Integrated Circuits for Optical Communications. McGraw-Hill: Behzad Razavi, 2003.
[6] A. X. Widmer, and P. A. Franaszek, ”A DC-balanced, partitioned-block, 8b/10b reansmission code,” IBM J. Res and Develop., vol. 27, pp. 440-451, Sep. 1983.
[7] S. H. Hall, G. W. Hall, and J. A. McCall, High-speed digital system design-Ahandbook of interconnect theory and design practices, John-Wiley, 1st ed., 2002
[8] Altera Corporation, “Deterministic Jitter (DJ) Definition and Measurement,” 2009
[9] Maxim, “Optical receiver performance evaluation”.
[10] SHF Communication Technologies AG, “Application Note AN-JITTER-1-Jitter Analysis using SHF 10000 Series Bit Error Rate Testers,” 2005.
[11] K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, and Y.-F. Lin, “A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 57 , no. 5 , pp. 324-328 , May. 2010.
[12] J. Lee, P.-C. Chiang, P.-J. Peng, L.-Y. Chen, and C.-C. Weng, “Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2061–2072, Sep. 2015.
[13] J. W. Jung, and B. Razavi, “A 25 Gb/s 5.8 mW CMOS Equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515–526, Feb. 2015.
[14] H. Wang, and J. Lee, “A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 909–920, Apr. 2010.
[15] S. Shahramian and A. C. Carusone, “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1722–1735, Feb. 2015.
[16] S. O. Haykin, Adaptive Filter Therory (5th Edition). Prentice Hall, 2002
[17] O. Elhadidy and S. Palermo, “A 10 Gb/s 2-IIR-Tap DFE Receiver with 35 dB Loss Compensation in 65-nm CMOS ,” in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2013, pp. C272–C273.
[18] S. Shahramian, B. Dehlaghi and A. C. Carusone, “Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 μs,” IEEE J. Solid-State Circuits, vol. 51, no. 1, pp. 3192–3203, Feb. 2016.
[19] Keysight, “M8048A ISI Channels - Data Sheet”.
[20] B. Kim, J. F. Bulzacchelli and D. J. Friedman, “A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44 , no. 12 , pp. 3526 - 3538 , Dec. 2009.
[21] Y.-C. Huang and S.-I. Liu, et al., “A 6Gb/s Receiver with 32.7dB Adaptive DFE-IIR Equalization,” ISSCC Dig. Tech. Papers, pp. 356-357, Feb. 2011.
[22] S. Shahramian, H. Yasotharan, and A. C. Carusone, “Decision feedback equalizer architectures with multiple continuous-time infinite impulse response filters,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 6, pp. 326–330, Jun. 2012.
[23] S. Son et al., “A 2.3-mW, 5-Gb/s low-power decision-feedback equalizer receiver front-end and its two-step, minimum bit-error-rate adaptation algorithm,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2693–2704,Nov. 2013.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2017-7-25

推文