多輸入多輸出前編碼系統之奇異值分解處理器設計與實現

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姓名

吳俊弘(Chun-Hung Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

多輸入多輸出前編碼系統之奇異值分解處理器設計與實現
(Design and Implementation of an SVD processor for MIMO precoding systems)

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摘要(中)

超大型多輸入多輸出系統(Large-scale multiple-input multiple-output system)被認為是第五代行動通訊系統的候選技術之一。在新的行動通訊系統中，基地台與使用者裝置所能使用的天線數量大幅提高，因此超大型多輸入多輸出系統相較於傳統的系統有著更高的運算複雜度。論文中主要是探討在此一系統中利用奇異質分解(singular value decomposition, SVD)求得前編碼矩陣的演算法，利用SVD可以將通道矩陣分解成數個互相不會干擾的子通道，而傳輸資料時會選擇通道增益較強的子通道進行傳輸。為了降低奇異值分解的運算複雜度，演算法分成三個階段，三個階段皆以Givens rotation為基礎，第一階段為雙對角化演算法，第二階段為Golub-Reinsch SVD演算法搭配矩陣劃分(split)和矩陣縮減(deflate)兩種機制，第三階段為位移QR演算法並搭配提前終止機制。所提出之演算法可以依照系統需求調整矩陣之收斂速度及所獲得奇異值之精確度。
而在硬體設計方面，則以支援到8×8的多輸入輸出系統為考量，因此主要根據第一階段與第二階段演算法完成奇異值分解之硬體設計，可以支援2×2∼8×8的矩陣維度，資料流格式採用外部浮點數內部定點數型式來表示，以精準涵蓋8×8通道矩陣的奇異值分布範圍，並且使用坐標軸旋轉數位計算器(Coordinate Rotation Digital Computer, CORDIC)，來實現Givens rotation的運算，CORDIC內部則有管線化(pipeline)設計，並將兩個CORDIC組成一個基礎的處理單元(processing element, PE)，來完成第一階演算法及第二階演算法，完成第一階段演算法的時脈週期數為171(clock cycles)，在第二階演算法其門檻值為2^(-3)的條件下，完成一個8×8的矩陣分解所需的時脈週期數313。我們透過TSMC 40nm製程將晶片設計實現，其最高時脈操作頻率為185MHz，吞吐量(Throughput)為每一秒可分解591K個矩陣(Matrix/s)。

摘要(英)

Large-scale MIMO (multiple-input multiple-output) technique is considered to be one of the promising solution in the 5th generation wireless communication system. Due to the increasing antenna number at both the transmitter and receiver sides, higher computational complexity is induced. Singular value decomposition (SVD) is a kind of decom-position scheme that is widely used to decompose the channel matrix into several spatial sub-channels. Usually the sub-channels with large channel gains (singular values) are chosen for transmission. A three-stage algorithm is used, and all can be accomplished by Givens rotation. Bi-diagonalization is employed at the first stage while Golub-Reinsch SVD with split and deflation is adopted at the second stage. We use shifted QR with early termination at the third stage. The SVD procedure can adjust the convergence speed and the accuracy according to the system requirements.
Considering SVD in 8×8 MIMO systems, the hardware implementation is mainly based on the first-stage and the second-stage operations. Our hardware can support channel matrix dimension from 2×2 to8×8. External floating-point and internal fixed-point representations are used for the datapath. The Givens rotation is realized by Coordinate Rotation Digital Computer (CORDIC). Two CORDIC modules constitute one processing element (PE). It takes 171 clock cycles for the first-stage operation and 313 clock cycles for the entire decomposition if the threshold for split and deflation at the second stage is set to 2^(-3). The hardware is implemented by TSMC 40nm CMOS technology. The maximum operating frequency is 185MHz and the throughput is 591K matrixes per second.

關鍵字(中)

★ 奇異值分解
★ 坐標軸旋轉數位計算器
★ 多輸入多輸出前編碼系統

關鍵字(英)

★ Singular value decomposition
★ Coordinate Rotation Digital Computer
★ MIMO precoding systems

論文目次

摘要 i
Abstract ii
目錄 iii
圖示目錄 vi
表格目錄 xi
第一章緒論 1
1.1. 簡介 1
1.2. 研究動機 1
1.3. 論文組織 2
第二章超大型多輸入多輸出系統(Large-scale MIMO System) 3
2.1. 系統模型(System Model) 3
2.2. 發送與接收端之天線陣列(Antenna array) 5
2.3. 奇異值分解前編碼矩陣(SVD Based MIMO Precoding Matrix) 8
2.4. 奇異值分解所使用之演算法(Algorithm of SVD) 10
2.4.1. Complex-value Given Rotation 演算法 11
2.4.2. Bidiagonalization 演算法 14
2.4.3. Implicit QR 演算法 18
第三章超大型多輸入多輸出奇異值分解前編碼系統(SVD Based Large-scale MIMO Precoding System) 23
3.1. 超大型多輸入多輸出奇異值分解前編碼系統之分析與流程(The Process and Analysis of SVD Based Large-scale MIMO Precoding System) 23
3.2. 第一階段演算法(The First Phase of SVD) 27
3.3. 第二階段演算法(The Second Phase of SVD) 29
3.4. 第三階段演算法(The Third Phase of SVD) 32
3.5. 演算法模擬(Simulation) 34
第四章奇異值分解硬體架構設計與實作(Hardware Design and Implementation of SVD) 38
4.1. 電路架構圖及介紹(Block Diagram of SVD Processor) 38
4.2. CORDIC架構(Hardware Architecture of CORDIC) 40
4.2.1. CORDIC硬體架構(CORDIC) 40
4.2.2. 數值動態範圍分析(Analysis of the Datapath Dynamic Range) 43
4.2.3. 浮點數資料流硬體架構(Floating-Point Data Paths) 46
4.3. 硬體控制及排程(Control and Schedule of Hardware) 52
4.3.1. CORDIC模式控制 52
4.3.2. Bidiagonalization排程及控制 54
4.3.3. GR SVD及Implicit QR with Shift Algorithm排程及控制 59
4.4. 記憶體架構及提取(Memory) 67
4.5. RTL模擬與C、Matlab模擬之比較(Compare RTL with C and Matlab) 71
第五章硬體實現 82
5.1. 硬體設計流程 82
5.2. 實作結果 85
5.2.1. Pre-layout Simulation 85
5.2.2. 晶片平面圖 88
5.2.3. LVS驗證結果 93
5.2.4. Post-layout Simulation 93
5.3. 硬體實作結果與比較 96
第六章結論 98
參考文獻 99

參考文獻

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指導教授

蔡佩芸(Pei-Yun Tsai)

審核日期

2017-8-9

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