以減少導線負載為目標的效能導向之類比電路繞線方法

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姓名

紀浩瑜(Hao-Yu Chi) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

以減少導線負載為目標的效能導向之類比電路繞線方法
(On Minimizing Wire Load of Analog Routing for Performance)

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摘要(中)

由於類比電路的敏感性，考量佈局後的非理想效應顯得更為重要。為降低非理想效應對電路效能的影響，類比電路設計大多會採用人工的方式產生佈局，因此需要耗費非常多的時間，雖然使用類比設計自動化工具可以節省設計的工作量，但眾多的佈局限制仍然是類比設計自動化發展的最大難題。除了佈局擺置的問題之外，目前也有一些類比電路繞線的相關文獻，然而大多數的方法還是採取數位電路的繞線模式，也就是在不同的金屬層使用偏好繞線方向的設定完成繞線。這種模式的繞線可以解決導線交錯的問題，但是在水平線與垂直線相連的地方就必須使用導孔來連接，因此會大幅的增加導線中的寄生效應，進而影響了電路的效能。
本論文提出一個在繞線階段將線阻最小化的類比設計自動化流程，希望在類比的繞線階段中盡可能地將導線用不換層的方式來完成，而在不換層的同時也需要考慮到線長等因素，使寄生效應降到最低，以確保電路能到達預定的規格。在繞線的過程中，首先針對繞線的路徑做初步的規劃，預估繞線的走向以及降低因為交錯而需要換層的情況發生，接著再將實際的繞線位置尋找出來，最後會用線長以及導孔的電阻值來計算線阻，透過尋找較少的線阻的繞線來做最佳化，而非僅依據線長，如同實驗數據所示，這方法確實可以使寄生效應對電路的影響降低，確保電路在佈局後能夠維持在預定的規格。

摘要(英)

Because analog circuits are often very sensitive, it is important to consider non-ideal effects in design stage. In order to reduce the impact of non-ideal effects on circuit performance, the layouts of analog circuits are often generated manually, which requires a lot of time. Using EDA tools is a possible way to reduce design efforts, but the complex layout constraints are still a big issue for layout automation. Besides the layout placement problem, there are some literatures on analog routing, too. However, most of the researches on analog layout automation are still using digital routing methodology that sets preferred routing direction for each metal layer. This routing methodology can solve the crossing issue between nets, but an extra via is required to connect the horizontal line and vertical line. Those vias will increase the non-ideal effects on routing nets and influence the circuit performance.
This thesis proposes an analog routing flow to minimize the wire resistance at routing stage. In the proposed method, we will try to route each net without changing metal layer and consider the wire length simultaneously to reduce the parasitic effect and keep circuit performance after layout. Frist, this flow will do a preliminary planning about the routing paths and their directions to reduce the layer changing cases due to net crossing. Next, the real routing paths are determined to calculate the wire resistance based on the number of vias and wire length. Instead of wire length, the wire resistance is used in the optimization to find the best path. As shown in the experimental results, this approach is able to reduce the parasitic effects on routing nets and keep the circuit performance after layout.

關鍵字(中)

★ 類比電路繞線

關鍵字(英)

★ Analog Routing

論文目次

摘要 i
Abstract iii
目錄 v
圖目錄 viii
表目錄 x
第一章、緒論 1
1-1 類比電路設計自動化 1
1-2 研究動機 3
1-3 問題定義 6
1-4 論文結構 7
第二章、背景知識 8
2-1 寄生效應 8
2-1-1 電晶體內部寄生效應 9
2-1-2 導線上寄生效應 9
2-1-3 電流及電阻所造成的電壓差 ( IR Drop ) 10
2-2 傳統繞線系統 12
2-2-1 全域繞線階段 12
2-2-2 細部繞線階段 13
2-3 繞線圖模型 14
2-3-1 網格繞線模型 14
2-3-2 非網格繞線模型 14
2-3-3 非正規網格繞線模型 15
2-4 繞線演算法 16
2-4-1 迷宮繞線 16
2-4-2 A*搜尋迷宮繞線 17
第三章、演算法流程 18
3-1 連線網路分解 19
3-1-1 建構繞線圖 19
3-1-2 多端點連線之分解 20
3-1-3 史坦納點(Steiner point)之調整 21
3-2 考量交錯之繞線 22
3-2-1 建立繞線區域 22
3-2-2 決定繞線走向 24
3-3 繞線路徑合法化 25
3-3-1 繞線圖的細化 25
3-3-2 搜尋實際繞線 26
3-4 線層分配 27
3-4-1 建構衝突樹 27
3-4-2 線層分配的初始與優化 27
3-5 佈局調整 30
3-5-1 微調較高層的導線 30
3-5-2 電阻最小化 31
第四章、實驗結果及分析 32
4-1 實驗環境與電路 32
4-2 兩級式運算放大器實驗結果 34
4-3 比較器實驗結果 34
第五章、結論與未來展望 42
參考文獻 43

參考文獻

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指導教授

劉建男(Chien-Nan Liu)

審核日期

2017-8-11

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