應用於C/X頻段互補式金氧半導體之寬頻升/降混頻器與四分之一週期之IQ發射機之研製

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姓名

郭品宏(Pin-Hung Kuo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於C/X頻段互補式金氧半導體之寬頻升/降混頻器與四分之一週期之IQ發射機之研製
(Implementations on Fully Integrated Wideband CMOS Up/Down Conversion Mixers and IQ Transmitter with 25%-Duty-Cycle LO Generation for C/X Band Applications)

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摘要(中)

本論文主要分兩部份，第一部分研究接收端之C/X頻段寬頻低功耗降頻器，第一顆利用tsmcTM 0.18 µm CMOS製程，使用倍頻器電路架構取得偶次項諧波訊號，並使用汲極注入技術，降低轉換損耗實現一寬頻低功耗次諧波被動降頻器。量測結果顯示，當本地振盪功率為 10 dBm時，轉換增益為 -6.7 dB，輸入功率1-dB壓縮點為1.5 dBm，二階交互調變失真點為39.5 dBm，三階交互調變失真點為 11.9 dBm，雙邊帶雜訊指數為10.8 dB，頻寬為6-12 GHz，總直流功率消耗為3.3 mW，晶片面積為0.87 × 0.93 mm2。
第二部份研究發射端之升頻器，第一顆晶片tsmcTM 0.18 µm CMOS製程，並採用被動電流模態混頻器以提高線性度之需求，並且利用電阻電容回授之差動疊接式前置驅動功率放大器將輸出功率提高，輸出端利用共振腔耦合技術設計一變壓器，實現寬頻功率匹配之效果，量測結果顯示本地振盪功率為4 dBm時，轉換增益為6.24 dB，輸出功率1-dB壓縮點為 -0.18 dBm，輸出端三階交互調變失真點為 9.6 dBm，本振埠與射頻埠之隔離度於頻帶內大於22.5 dB，3-dB頻寬為5-12.4 GHz，直流功率消耗為79.8 mW，晶片面積為1.53 × 0.95 mm2。
第二顆晶片為一應用於C頻段IQ發射機，利用tsmcTM 0.18 µm CMOS製程，使用除頻器與四分之一週期產生器產生四相位本振源，並且設計一同相與正交訊號結合之電流放大器將I路與Q路訊號結合，有效抑制靜象訊號頻率，量測結果顯示本地振盪功率為10 dBm時，轉換增益為-4.67 dB，頻帶內邊通帶抑制為5.17 dBc，本振埠漏訊號抑制為-25.1 dBc。由於量測結果與模擬相差甚大，故無量測其餘大訊號參數之價值，量測之直流功率消耗為128.4 mW，晶片面積為1.61 × 1.16 mm2。

摘要(英)

For supporting an ever-increasing number of cellular handset users, RF transceivers for the 5th generation of wireless communication system need to deliver the demands of broad bandwidth and high data rates. Moreover, low cost, low power consumption, and high integration are also the proliferating requirements in wireless transceiver design for next generation mobile handsets. A mixer is one of the essential sub-circuits in receivers and transmitters to complement the frequency translation. This thesis based on mixer design can mainly contains five parts, namely the motivation, two wideband mixers for C/X band applications, a quadrature transmitter for 5 GHz, and the future work.
The first work in Chapter 2 is fabricated in tsmcTM 0.18 μm CMOS technology. The author applied a frequency doubler for sub-harmonic pumping technique whose local (LO) frequency is an half of the desired RF frequency. This proposed mixer is adopted passive architecture and driven by drain port, leading to improved performances in terms of power consumption, noise, linearity, and conversion loss. The experimental results are described as follow, a conversion loss of 6.7 dB, input 1-dB compression point of 1.5 dBm, an IIP2 of 39.5 dBm, an IIP3 of 11.9 dBm, and a double sideband (DSB) noise figure (NF) of 10.8 dB with 0 dBm LO drive power. Due to doubly balanced configuration, the proposed mixer achieved outstanding isolation performance of better than 30 dB. The 3-dB bandwidth is measured from 6 to 12 GHz and total dc power dissipation of 3.3 mW at 1.5-V supply. The die size is 0.87 × 0.93 mm2.
The second work in Chapter 3 is implemented in tsmcTM 0.18 μm CMOS technology. For the purpose of enhanced linearity and mitigated noise, the conventional Gilbert upconversion mixer is replaced by a passive current mode mixer. In addition, a differential pair of cascode power amplifier driver with RC feedback is presented following the passive mixer to provide medium output power in the transmitter chain. By using resonator coupling technique, the transformer is successfully demonstrated and realized the wideband power matching for the previous power amplifier driver to meet the optima output power. The proposed upconversion mixer exhibits the measured conversion gain of 6.24 dB, output 1-dB compression point of -0.18 dBm and OIP3 of 9.6 dBm under the LO power of 4 dBm. The LO-to-RF isolation is better than 22.5 dB within the desired 3-dB bandwidth from 5 to 12.4 GHz. The chip consumes the dc power of 79.8 mW and occupies 1.53 × 0.95 mm2.
In Chapter 4, a transmitter prototype incorporated with quadrature mixer, 25% duty-cycle LO generation, and power amplifier driver is designed and fabricated in standard 0.18 μm CMOS technology. To eliminate the side-band frequency without any integrated sideband-reject filters, a quadrature mixer, which mixes the in-phase (I) and quadrature (Q) input baseband frequency signals with in-phase and quadrature phase LO signals. The frequency divider of current mode logic is widely and practically applied to generate quadrature signals, LO_I+, LO_I-, LO_Q+, LO_Q-. Furthermore, a passive current mixer switching with 25% duty-cycle LO is presented, which improves 3 dB higher conversion gain, better NF, and the flicker noise less than that switching with 50% duty-cycle LO. The IQ transmitter demonstrates measured conversion gain of -4.67 dB, which is biased at 1.8-V and dissipates 128.4 mW. The measured LO suppression and sideband suppression are -25.1dBc and 5.17 dBc, respectively. All aforementioned measured results are under LO input power equal to 10 dBm. The die size is 1.61 × 1.16 mm2 and will be bonded to the printed-circuit board (PCB) for testing.

關鍵字(中)

★ 寬頻
★ 降頻器
★ 低功耗
★ 升頻器
★ IQ發射機
★ 除頻器
★ 四分之一週期

關鍵字(英)

★ Wideband
★ Down-conversion Mixer
★ Low power
★ Up-conversion Mixer
★ IQ transmitter
★ CML
★ 25% duty cycle

論文目次

摘要 I
Abstract II
誌謝 IV
目錄 VI
圖目錄 VIII
表目錄 X
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節敘述 2
第二章使用倍頻器與汲極注入之寬頻低功耗次諧波降頻器 3
2-1 前言 3
2-2 電路架構與原理 3
2-3 模擬與量測結果 9
2-4 結果與討論 19
第三章應用於C/X頻段射頻前端發射機之寬頻升頻器 21
3-1 前言 21
3-2 電路架構與原理 24
3-2-1 電流模態被動混頻器簡介 24
3-2-2 電壓電流轉換之反相轉導放大器與前置驅動放大器之設計 29
3-2-3 共振腔耦合之變壓器設計 30
3-3 模擬與量測結果 35
3-4 結果與討論 41
第四章使用除頻器與四分之一週期產生器之C頻段IQ發射機 44
4-1 前言 44
4-2 電路架構與原理 46
4-2-1 除頻器設計 48
4-2-2 四分之一週期產生器簡介與設計 50
4-2-3 同相與正交訊號結合之電流放大器 54
4-3 模擬結果 56
4-4 結果與討論 68
第五章結論 70
5-1 結論 70
5-2 未來期許與研究方向 71
References 72

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指導教授

邱煥凱(Hwanne Kaeo Chiou)

審核日期

2017-8-11

推文