基於高壓製程的高速位準轉換器設計

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駱祈宏(Chi-Hung Lo) 查詢紙本館藏

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電機工程學系

論文名稱

基於高壓製程的高速位準轉換器設計
(High speed level shifter design based on high voltage BCD process)

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摘要(中)

本論文基於栓鎖式電壓位準轉換電路提出兩種新型適用於高電壓位準轉換器電路架構，並使用高壓製程中的功率電晶體作為電壓隔離器件設計電路。由於功率元件當作高壓隔離開關切換時存在米勒平台效應造成延遲，因此本論文提出利用電阻負載式以及電阻負載稽納二極體式兩種高壓位準轉換器結構，希冀能增加電壓位準轉換的速度。另外，為了解高壓製程中DPW_NBL隔絕環是否在不同逆向偏壓時對轉換器性能造成的影響，在電路中低壓區域的N+深埋層以及高壓區域的N+深埋層分別施以相同以及不同的電壓值以探討差異。為驗正本文提出的位準轉換器架構性能，本論文分別設計並量測三種不同結構的電壓轉換上升電路以電壓轉換下降電路，其中使用TSMC 0.25-um 60-V Bipolar-CMOS-DMOS(BCD) 高壓製程實現高電壓位準轉換器，最後比較轉換器性能以及建立效能指數(FOM)分析。文中所設計的電壓轉換上升位準轉換器可將輸入信號0到5V電壓，頻率為5MHz方波平移為正20V到正25V的方波，總共用於分析比較的七組轉換器整體晶片面積為2603 um X 611um；而電壓轉換下降位準轉換器可將輸入信號0到5V電壓，頻率為5MHz的方波平移為負20V到負25V的方波，7組轉換器整體晶片面積為2595.7 um X 649.4um。

摘要(英)

Two novel level-shifter architectures based on cross-coupled latch pairs for high voltage level-shifter applications was proposed and analyzed in this thesis. Since high votlage power transistors were employed as isolated protection devcies inside the level shifters, and the delay caused by Miller effect exists while power transistors switch on and off, two different high voltage level shilfters with resisitive loading and zener diode in series with a resistor, respectively, were designed to increase the transtion speed of the level shifters. In addition, to understand the roles of DPW_NBL isolated ring of the high votlage process while different reverse bias votlage applied with and effects on the performance of the level shifters, the N+ deep burried layer in the low voltage region and the high voltage region, respectively, were applied with the same and different voltage levels, separately, to examine the effects. In order to verify the proposed architectures, three kinds of different high voltage level shifters, including level-shifting from low voltage to high voltage, and high voltage to low voltage, were designed using TSMC 0.25um 60V Bipolar-CMOS-DMOS (BCD) process. The performance matrix (Figure of merit) was built and analyzed. The designed 7 different level-shifter circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a 20 ~ 25V square wave occupy total area of 2603um x 611um, and the other 7 circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a -20 ~ -25V square wave occupy the area of 2595.7um x 649.4um, respectively.

關鍵字(中)

★ 位準轉換器設計
★ 整合式雙極性/互補金氧半元件/擴散式金氧半元件
★ N+深埋層

關鍵字(英)

★ level-shifter
★ Bipolar-CMOS-DMOS
★ N-buried Layer

論文目次

摘要ii
Abstract iii
誌謝v
目錄vi
圖目錄 xii
表目錄 xviii
第一章緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 4
第二章高壓BCD製程暨元件介紹 5
2.1 BCD製程介紹 5
2.1.1 BCD種類 7
2.1.2 元件隔離技術 11
2.1.2.1 自我絕緣技術 11
2.1.2.2 接面絕緣技術 12
2.1.2.3 介電質絕緣技術 13
2.2 元件介紹 14
2.2.1 N型橫向擴散金屬氧化物半導體架構 15
2.2.2 P型橫向擴散金屬氧化物半導體架構 17
第三章高壓位準轉換器架構 19
3.1 電阻負載稽納二極體式高壓上升位準轉換器 19
3.2 高壓上升位準轉換器結構 24
3.2.1 主動式箝位高壓上升位準轉換器 26
3.2.2 電阻負載式高壓上升位準轉換器 30
3.2.3 快速低功耗高壓上升位準轉換器 32
3.3 總結 34
第四章高壓高速位準轉換器設計 35
4.1 高壓上升位準轉換器設計 35
4.1.1 主動式箝位高壓上升位準轉換器 35
4.1.2 電阻負載式高壓上升位準轉換器 38
4.1.3 電阻負載稽納二極體式高壓上升位準轉換器 41
4.2 高壓下降位準轉換器設計 45
4.2.1 主動式箝位高壓下降位準轉換器 45
4.2.2 電阻負載式高壓下降位準轉換器 48
4.2.3 電阻負載稽納二極體式高壓下降位準轉換器 51
4.3 接面絕緣技術(電壓測試) 55
第五章高壓高速位準轉換器模擬 57
5.1 高壓上升位準轉換器結構(前模擬不包含寄生電容) 58
5.1.1 主動式箝位高壓上升位準轉換器 58
5.1.1.1 相同N+深埋層電壓以及包含ESD 59
5.1.1.2 不相同N+深埋層電壓以及包含ESD 62
5.1.2 電阻負載式高壓上升位準轉換器 65
5.1.2.1 相同N+深埋層電壓以及包含ESD 66
5.1.2.2 不相同N+深埋層電壓以及包含ESD 69
5.1.3 電阻負載稽納二極體式高壓上升位準轉換器 72
5.1.3.1 相同N+深埋層電壓以及包含ESD 73
5.1.3.2 不相同N+深埋層電壓以及包含ESD 76
5.1.3.3 不相同N+深埋層電壓以及不包含ESD 79
5.1.4 電路表現分析 82
5.2 高壓下降位準轉換器結構(前模擬不包含寄生電容) 85
5.2.1 主動式箝位高壓下降位準轉換器 85
5.2.1.1 相同N+深埋層電壓以及包含ESD 86
5.2.1.2 不相同N+深埋層電壓以及包含ESD 89
5.2.2 電阻負載式高壓下降位準轉換器 92
5.2.2.1 相同N+深埋層電壓以及包含ESD 93
5.2.2.2 不相同N+深埋層電壓以及包含ESD 96
5.2.3 電阻負載稽納二極體式高壓下降位準轉換器 99
5.2.3.1 相同N+深埋層電壓以及包含ESD 100
5.2.3.2 不相同N+深埋層電壓以及包含ESD 103
5.2.3.3 不相同N+深埋層電壓以及不包含ESD 106
5.2.4 電路表現分析 109
5.3 高壓上升位準轉換器結構(後模擬包含寄生電容電阻) 112
5.3.1 主動式箝位高壓上升位準轉換器 112
5.3.1.1 相同N+深埋層電壓以及包含ESD 113
5.3.1.2 不相同N+深埋層電壓以及包含ESD 116
5.3.2 電阻負載式高壓上升位準轉換器 119
5.3.2.1 相同N+深埋層電壓以及包含ESD 120
5.3.2.2 不相同N+深埋層電壓以及包含ESD 123
5.3.3 電阻負載稽納二極體式高壓上升位準轉換器 126
5.3.3.1 相同N+深埋層電壓以及包含ESD 127
5.3.3.2 不相同N+深埋層電壓以及包含ESD 130
5.3.3.3 不相同N+深埋層電壓以及不包含ESD 133
5.3.4 電路表現分析 136
5.4 高壓下降位準轉換器結構(後模擬包含寄生電容電阻) 139
5.4.1 主動式箝位高壓下降位準轉換器 139
5.4.1.1 相同N+深埋層電壓以及包含ESD 140
5.4.1.2 不相同N+深埋層電壓以及包含ESD 143
5.4.2 電阻負載式高壓下降位準轉換器 146
5.4.2.1 相同N+深埋層電壓以及包含ESD 147
5.4.2.2 不相同N+深埋層電壓以及包含ESD 150
5.4.3 電阻負載稽納二極體式高壓下降位準轉換器 153
5.4.3.1 相同N+深埋層電壓以及包含ESD 154
5.4.3.2 不相同N+深埋層電壓以及包含ESD 157
5.4.3.3 不相同N+深埋層電壓以及不包含ESD 160
5.4.4 電路表現分析 163
5.5 規格比較 166
5.5.1 高壓上升位準轉換器結構 167
5.5.2 高壓下降位準轉換器結構 169
第六章晶片佈局與量測考量 171
6.1 晶片佈局 171
6.1.1 晶片封裝 173
6.1.2 佈局規劃 175
6.2 晶片照相與量測環境設定 175
6.3 高壓上升位準轉換器結構(量測結果) 178
6.3.1 主動式箝位高壓上升位準轉換器相同N+深埋層電壓以及包含ESD 178
6.3.2 主動式箝位高壓上升位準轉換器不相同N+深埋層電壓以及包含ESD 180
6.3.3 主動式箝位高壓上升位準轉換器比較 182
6.3.4 電阻負載式高壓上升位準轉換器相同N+深埋層電壓以及包含ESD 183
6.3.5 電阻負載式高壓上升位準轉換器不相同N+深埋層電壓以及包含ESD 185
6.3.6 電阻負載式高壓上升位準轉換器比較 187
6.3.7 電阻負載稽納二極體式高壓上升位準轉換器相同N+深埋層電壓以及包含ESD 188
6.3.8 電阻負載稽納二極體式高壓上升位準轉換器不相同N+深埋層電壓以及包含ESD 190
6.3.9 電阻負載稽納二極體式高壓上升位準轉換器不相同N+深埋層電壓以及不包含ESD 192
6.3.10 電阻負載稽納二極體式高壓上升位準轉換器比較 194
6.4 高壓下降位準轉換器結構(量測結果) 195
6.4.1 主動式箝位高壓下降位準轉換器相同N+深埋層電壓以及包含ESD 195
6.4.2 主動式箝位高壓下降位準轉換器不相同N+深埋層電壓以及包含ESD 197
6.4.3 主動式箝位高壓下降位準轉換器比較 199
6.4.4 電阻負載式高壓下降位準轉換器相同N+深埋層電壓以及包含ESD 200
6.4.5 電阻負載式高壓下降位準轉換器不相同N+深埋層電壓以及包含ESD 202
6.4.6 電阻負載式高壓下降位準轉換器比較 204
6.4.7 電阻負載稽納二極體式高壓下降位準轉換器相同N+深埋層電壓以及包含ESD 205
6.4.8 電阻負載稽納二極體式高壓下降位準轉換器不相同N+深埋層電壓以及包含ESD 207
6.4.9 電阻負載稽納二極體式高壓下降位準轉換器不相同N+深埋層電壓以及不包含ESD 209
6.4.10 電阻負載稽納二極體式高壓下降位準轉換器比較 211
6.5 規格比較 212
6.5.1 高壓上升位準轉換器結構 213
6.5.2 高壓下降位準轉換器結構 215
第七章結論與未來研究方向 217
參考文獻 218

參考文獻

[1] IoT晶片設計的商機與挑戰
From:http://www.naipo.com/Portals/1/web_tw/Knowledge_Center/Research_Development/publish-86.htm
[2] IoT-Umsatze leicht nach unten korrigiert
From:http://www.elektroniknet.de/markt-technik/industrie-40-iot/iot-umsaetze-leicht-nach-unten-korrigiert-142353.html
[3] Gauging the High-Accuracy 60-V Gas Gauge
From:http://www.powerelectronics.com/automotive/loss-battery-cable-isolation-prompts-evhevs-protect-against-potential-hazard
[4] ICs to bring longer battery life to portable devices
From:http://www.newelectronics.co.uk/electronics-technology/ics-to-bring-longer-battery-life-to-portable-devices/155489/
[5] Boost Appliance Efficiency with Low-Voltage BLDCs
From:http://www.electronicdesign.com/power/boost-appliance-efficiency-low-voltage-bldcs
[6] J. F. D. Rocha, M. B. D. Santos, J. M. D. Costa, F. A. Lima, ”Level shifters and DCVSL for a low-voltage CMOS 4.2-V buck converter”, IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3315-3323, Sep. 2008.
[7] Y.-M. Li, C.-B. Wen, B. Yuan, L.-M. Wen, Q. Ye, ”A high speed and power-efficient level shifter for high voltage buck converter drivers”, Proc. IEEE Int. Conf. Solid-State Integr. Circuit Tech, pp. 309-311, 2010.
[8] Ping-Yeh Yin, Chih-Wen Lu,Yuan-Ho Chenu, Hsin-Chin Liang, Sheng-Pin Tseng, “A 10-Bit Low-Power High-Color-Depth Column Driver With Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs,” Journal of Display Technology , vol;. 11, no. 12, pp. 1061 - 1068,Dec 2015.

[9] Fangfang Yang, Cuicui Wang, Hing-Mo Lam, Qiang Zhao, Jia Fan, Shengdong Zhang, ”A floating high-voltage level shifter used in a pre-charge circuit for large-size AMOLED displays”, Electron Devices and Solid-State Circuits (EDSSC) 2016 IEEE International Conference on, pp. 267-270, 2016.
[10] Hyouk-Kyu Cha, Dongning Zhao, Jia Hao Cheong, Bin Guo, Hongbin Yu, Minkyu Je, ”A CMOS High-Voltage Transmitter IC for Ultrasound Medical Imaging Applications”, Circuits and Systems II TCSII, vol. 60, pp. 316-320, 2013.
[11] S.Vaishnavi, S.Ashok, T.Mohammed Abbas, Arun Ragesh, Dr.Rangarajan Dr.Sakunthala, ”Design and Analysis of Level Shifter in High Voltage Transmitter”,International Journal of Scientific and Research Publications, Volume 4, Issue 1, January 2014 ISSN 2250-3153
[12] D. Pan, H. Li, B. Wilamowski, ”A low voltage to high voltage level shifter circuit for MEMS application”, Proc. 15th Biennial Univ./Government/Ind. Microelectron. Symp., pp. 128-131, 2003-Jul.
[13] Hao-Yen Tang, ”High Voltage Level-Shifter Circuit Design for Efficiently High Voltage Transducer Drivin”,EECS Department University of California, Berkeley Technical Report No. UCB/EECS-2014-203 December 1, 2014
from: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-203.html
[14] Nicolas Laflamme-Mayer, Mathieu Renaud, ”A novel high-voltage 5.5 V resilient floating and full-scale 3.3 V pulse-triggered level-shifter”, Circuits and Systems (ISCAS) 2016 IEEE International Symposium on, pp. 2242-2245, 2016, ISSN 2379-447X.
[15] Michael Haas, Maurits Ortmanns, ”A floating high-voltage level-shifter with high area efficiency for biomedical implants”, Ph.D. Research in Microelectronics and Electronics (PRIME) 2016 12th Conference on, pp. 1-4, 2016.
[16] 陳謙之著/鄭桂忠博士指導教授, “ 以標準0.18μm CMOS製程製作附有電流校正機制之12V-500μA神經刺激器/A 12V-500μA Neuron Stimulator implemented in Standard 0.18μm CMOS Process with Current Calibration Mechanism”,新竹市/國立清華大學/2011

[17] J.-M. Baek, J.-H. Chun, K.-W. Kown, ”A Power Efficient Voltage Upconverter for Embedded EEPROM Application”, IEEE Trans. Circuits and Systems-H: Express Briefs, vol. 57, no. 6, pp. 435-439, 2010.
[18] Junhua Liu, Le Ye, Zhixin Deng, Jinshu Zhao, Huailin Liao, ”A 1.8V to 10V CMOS level shifter for RFID transponders”, Solid-State and Integrated Circuit Technology (ICSICT) 2010 10th IEEE International Conference on, pp. 491-493, 2010.
[19] Michael Haas, Maurits Ortmanns, ”A floating high-voltage level-shifter with high area efficiency for biomedical implants”, Ph.D. Research in Microelectronics and Electronics (PRIME) 2016 12th Conference on, pp. 1-4, 2016.
[20] B.Murari, F.Bertotti, and G.A.Vignola, “Smart Power ICs”.
[21] B.J. Baliga, “Power Semiconductor Devices”.
[22] Antonio Imbruglia,” BCD and discrete technologies for power management ICs development”, European Space Components Conference (ESCCON), March 14,2013.
From: https://escies.org/webdocument/showArticle?id=962&groupid=6
[23] B.Murari, C. Contiero, R. Gariboldi, S. Sueri, A. Russo, “Smart Power Technologies Evolution”, Industry Application Conference, pp. 10-19,2000.
[24] R. Bashir ,F. Hebert , J. DeSantis , J.M. McGregor , W. Yindeepol , K. Brown , F. Moraveji , T.B. Mills ; A. Sadovnikov ; J. McGinty ; P. Hopper, “A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications,” IEEE Transactions on Electron Devices,vol;48,no.11,pp. 2525 – 2534, Nov 2001.
[25] F. Berta , S. Hidalgo , P. Godignon , J. Rebollo , J. Millan, “A simplified low voltage smart power technology,”Electrotechnical Conference,1991.Proceedings.,6th Mediterranean,22-24 May 1991.
[26] 邱筱芸著/金雅琴指導教授、林崇榮共同指導教授, “應用於高端驅動器的電位移轉器研究/The Study of a Level Shifter for High Side Gate Drive IC”,新竹市/國立清華大學/2010
[27] STMicroelectronics, Retrieved March 05, 2017, from http://www.st.com/content/st_com/zh.html
[28] C. Contiero, A. Andreini, and P. Galbiati, ”Roadmap Differentiation and Emerging Trends in BCD Technology,” Proc. ESSDERC, pp.275-282, September 2002.
[29] C. Contiero, P. Galbiati, A. Merlini, A. Moscatelli, F. Tampellini, L. Vecchi, ”Trend and issues in BCD smart power technologies”, Proc. 28th Eur. Solid-State Device Research Conf. (ESSDERC99), pp. 111-118, 1999.
[30] Jean-Marc Chery,” Technology & Manufacturing”, Chief Operating Officer. 17.May.2017
From: http://investors.st.com/phoenix.zhtml?c=111941&p=irol-calendarpast
[31] 130nm BCDLiteR & BCD
From:https://www.globalfoundries.com/sites/default/files/product-briefs/130nm-bcd-lite-technology-product-brief.pdf
[32] 陳志勇,黃其煜,龔大衛,”BCD工藝概述”, 半導體技術,第31卷2006第9期.
From:http://www.61ic.com/code/attachment.php?aid=47125&k=b48848fc554230209365516ededdbbaa&t=1371959833
[33] 楊銀堂,朱海鋼,” BCD 集成電路技術的研究與發展”,微電子學,第36卷2006年第三期
From:http://www.61ic.com/code/attachment.php?aid=47126&k=95fb4d5b44a2d89ca762ecc72cec5f2f&t=1363844264
[34] 物聯網時代不可或缺的要角－功率放大器(PA)
From:https://www.stockfeel.com.tw/%E7%89%A9%E8%81%AF%E7%B6%B2%E6%99%82%E4%BB%A3%E4%B8%8D%E5%8F%AF%E6%88%96%E7%BC%BA%E7%9A%84%E8%A6%81%E8%A7%92%EF%BC%8D%E5%8A%9F%E7%8E%87%E6%94%BE%E5%A4%A7%E5%99%A8pa/
[35] Yongcheol Choi ,Changki Jeon ,insuk KimJkgjgwsg, “Design and process considerations for 1200V HVIC technology,” Power Semiconductor Devices & IC′s, 2009. ISPSD 2009. 21st International Symposium on, 14-18 June 2009.

[36] Sung-Lyong Kim, Chang-Ki Jeon, Min-Suk Kim, Jong-Jib Kim, “1200V Interconnection Technique with Isolated Self-Shielding Structure”, Power Semiconductor Devices and IC′s 2006. ISPSD 2006. IEEE International Symposium on, pp. 1-4, 23-26 Oct 2006.
[37] Rudy Octavius Sihombing, Gene Sheu, Shao-Ming Yang, Hutomo Suryo Wasisto, Yu-Feng Guo, Shang-Hui Tu, Yu-Lung Chin, Jin-Shyong Jan, Chia-Hao Lee, “An 800 volts high voltage interconnection level shifter using Floating Poly Field Plate (FPFP) method”, TENCON 2010 - 2010 IEEE Region 10 Conference, pp. 71-74, 21-24 Nov 2010.
[38] Weifeng Sun, Jing Zhu, Long Zhang, Hui Yu, Yicheng Du, Keqin Huang, Shengli Lu, Longxing Shi, Yangbo Yi, ”A Novel Silicon-on-Insulator Lateral Insulated-Gate Bipolar Transistor With Dual Trenches for Three-Phase Single Chip Inverter ICs”, Electron Device Letters IEEE, vol. 36, pp. 693-695, 18 May 2015.
[39] E. Ophir Arad, A. Parag, E. Aloni, A. Eyal, Y. Choi, S. Shapira, “Junction isolation for high voltage integrated circuits”, Electrical & Electronics Engineers in Israel (IEEEI) 2012 IEEE 27th Convention of, pp. 1-4, 14-17 Nov 2012.
[40] J. A. Appels and H. M. J. Vaes, ”High voltage thin layer devices (RESURF devices),” in IEEE International Electron Devices Meeting, Washington, pp. 238-241 3-5 Dec. 1979.
[41] 傅士豪著/龔正指導教授黃智方指導教授, “LDMOSFET特性分析極其模型的建立/ Analysis and Model Establishment of N-type Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET)”,新竹市/國立清華大學/2009.
[42] 張興政著/蔡銘裕指導教授, “絕緣磊晶橫向功率電晶體智慧型模組設計與實現 / The Development of the Smart SOI LIGBT Module ”,台中市/私立逢甲大學/2000.
[43] 紀雅軒著/龔正指導教授, “以雙層磊晶技術研製超高壓低漏電流橫向絕緣閘雙極性電晶體(LIGBT)/ The Study on Ultra High Voltage Low Substrate Current LIGBT with Double Epitaxial Layer Technology ”,台中市/私立東海大學/2014.
[44] 蘇建仁/張隆國指導教授,“功率積體電路之接面隔離研究/Study on the Junction Isolation of Power Integrated Circuits”, 新竹市/國立交通大學/2004.
[45] OLIVER TRIEBL ,“Reliability Issues in High-Voltage Semiconductor Devices”, Retrieved March 25, 2017, from http://www.iue.tuwien.ac.at/phd/triebl/.
[46] Mariam Sadaka,“S3 s short course intro soi apps (1)”, Retrieved March 25, 2017,from https://www.slideshare.net/cddsoitec/s3-s-short-course-intro-soi-apps-1-54477165
[47] C.-L. Chen, D.-S. Wang, J.-J. Li, C.-C. Wang, ”A voltage monitoring IC with HV multiplexer and HV transceiver for battery management systems”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 23, no. 2, pp. 244-253, Feb. 2015.
[48] Andrey A. Antonov, Maksim S. Karpovich, Igor V. Pichugin, Vladislav Yu. Vasilyev, ”“In silicon” verification of Multi-Functional Control Integrated Circuits in 250 nm BCD technology for high-efficiency power converters”, Actual Problems of Electronics Instrument Engineering (APEIE) 2016 13th International Scientific-Technical Conference on, vol. 03, pp. 83-87, 2016.
[49] Z. Y. Tu, L. J. Wu, X. M. Zhang, L. Y. Pan, ”A low power 64K-bit eeprom for battery-less TPMS SoC”, Solid-State and Integrated Circuit Technology (ICSICT) 2014 12th IEEE International Conference on Guilin, pp. 1-3, 2014.
[50] 許健,楊紹明,”高壓元件動態性安全操作範圍”
From: http://www.edma.org.tw/doc/Magazine_20-2-1.pdf
[51] 黃楀晴/柯明道指導教授,” 高壓製程之靜電放電防護元件設計/Study of Electrostatistic Discharge Protection Devices in High-Voltage BCD Processes” , 新竹市/國立交通大學/2014
[52] Shen-Li Chen, Yu-Ting Huang, ”Drain-side discrete-distributed layout influences on reliability issues in the 0.25 μm 60-V power pLDMOS”, Power Electronics and ECCE Asia (ICPE-ECCE Asia) 2015 9th International Conference on, pp. 581-587, 2015, ISSN 2150-6086.
[53] Y. Moghe, T. Lehmann, and T. Piessens, “Nanosecond delay floating high voltage level shifters in a 0.35 mu m hv-cmos technology,” IEEE JOURNAL OF SOLID-STATE CIRCUITS ’’, vol. 46, no. 2, pp. 485-497, 10 December.2011.

[54] D. Pan, H. W. Li, B. M. Wilamowski, “A low voltage to high voltage level shifter circuit for MEMS application’’, Proc. 15th Biennial University/Government/Industry Microelectronics Symp, pp. 128-131, 2003.
[55] Z. Liu, H. Lee, “A synchronous LED driver with dynamic level-shifting and simultaneous peak & valley current sensing for high-brightness lighting applications’’, Proc. IEEE MWSCAS, pp. 125-128, Aug. 2013.
[56] M. Khorasani, L. van den Berg, P. Marshall, M. Zargham, V. Gaudet, D. Elliott, S. Martel, “Low-power static and dynamic high-voltage cmos level-shifter circuits’’, Proc. IEEE Int. Symp. Circuits and Systems (ISCAS 2008), pp. 1946-1949, May.2008.
[57] M. A. Huque, L. M. Tolbert, B. J. Blalock, S. K. Islam, “Silicon-on-insulator-based high-voltage high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors’’, IET Power Electron., vol. 3, no. 6, pp. 1001-1009, Nov. 2010.
[58] T. Lehmann, ”Design of fast low-power floating high-voltage levelshifters.” Electronics Letters, vol. 50, no. 3, p. 1, 2014.
[59] Liu Dawei, S.I. Hollis, B.H. Stark, “A new circuit topology for floating High Voltage level shifters’’, PRIME, pp. 1-4, 2014.
[60] Dawei Liu, Simon J. Hollis, Harry C. P. Dymond, Neville McNeill, Bernard H. Stark, “Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance’’, Circuits and Systems II: Express Briefs IEEE Transactions on, vol. 63, pp. 688-692, 2016.
[61] Dr.Phillip.Allen,CMOS Analog IC Design Short Course,RetrievedMarch05,2017, From:http://www.aicdesign.org/SCNOTES/2010notes/Lect2UP100_(100324).pdf
[62] W.-K. Park, C.-U. Cha, S.-C. Lee, “A novel level-shifter circuit design for display panel driver’’, Proc. IEEE MWSCAS, pp. 391-394, Aug. 2006.

[63] Seyed Rasool Hosseini, Mehdi Saberi, Reza Lotfi, ”A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications”, Very Large Scale Integration (VLSI) Systems IEEE Transactions on, vol. 25, pp. 1154-1158, 2017, ISSN 1063-8210.
[64] Richard C. Dorf , The Electrical Engineering Handbook,Second Edition,1997.
[65] vishay, Retrieved March 05, 2017.
From: http://www.vishay.com/docs/73217/an608a.pdf
[66] vishay, Retrieved March 05, 2017.
From: http://www.vishay.com/docs/71946/an605cn.pdf
[67] Baliga, B. Jayant, Fundamentals of Power Semiconductor Devices, 2008.
[68] M. A. H. Broadmeadow, G. F. Ledwich, G. R. Walker, “An improved gate driver for power MOSFETs using a cascode configuration’’, Power Electronics Machines and Drives (PEMD 2014) 7th lET International Conference on, pp. 1-6, April 2014.
[69] Baker, R. Jacob/ Li, Harry W./ Boyce, David E. “Cmos Circuit Design, Layout, and Simulation’
[70] CMOS Power Consumption and Cpd Calculation
From: http://www.ti.com/lit/an/scaa035b/scaa035b.pdf
[71] CMOS Power Consumption and Cpd Calculation
From: http://www.ti.com/lit/an/scaa035b/scaa035b.pdf
[72] Paulo Francisco Butzen and Renato Perez Ribas,” Leakage Current in Sub-Micrometer CMOS Gates”.
From: http://www.inf.ufrgs.br/logics/docman/book_emicro_butzen.pdf
[73] K. Roy, S. Mukhopadhyay, H. M. Meimand, ”Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, February 2003.
[74] PAULO FRANCISCO BUTZEN / Prof. Dr. Renato Perez Ribas, Leakage Current Modeling in Submicrometer CMOS Complex Gates.
From: http://livros01.livrosgratis.com.br/cp141757.pdf
[75] K. K. Kim, Y. B. Kim, M. Choi, N. Park, ”Leakage minimization technique for nanoscale CMOS VLSI”, IEEE Design and Test of Computers, vol. 24, no. 4, pp. 322-330, Aug. 2007
[76] Voltage Translation Between3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards
From: http://www.ti.com/lit/an/scea030b/scea030b.pdf
[77] Digital Integrated Circuits
From: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/notes.html

指導教授

夏勤(Chin Hsia)

審核日期

2017-8-24

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