K頻段互補式金氧半場效電晶體低功耗低相位雜訊四相位時脈產生器之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：28

、訪客IP：18.223.32.230

姓名

沈毅恩(Ian Shen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

K頻段互補式金氧半場效電晶體低功耗低相位雜訊四相位時脈產生器之研製
(Design of K-band CMOS Low Power Low Phase Noise Quadrature Clock Generator)

相關論文

★ 微波及毫米波切換器及四相位壓控振盪器整合除三除頻器之研製	★ 微波低相位雜訊壓控振盪器之研製
★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統	★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
★ 微波及毫米波行進波切換器之研製	★ 寬頻低功耗金氧半場效電晶體射頻環狀電阻性混頻器
★ 微波與毫米波相位陣列收發積體電路之研製	★ 24 GHz汽車防撞雷達收發積體電路之研製
★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究	★ 高功率高效率放大器與振盪器研製
★ 微波與毫米波寬頻主動式降頻器	★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
★ 寬頻主動式半循環器與平衡器研製	★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
★ 銻化物異質接面場效電晶體之研製及其微波切換器應用	★ 微波毫米波寬頻振盪器與鎖相迴路之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在射頻收發系統中，本地振盪源扮演極重要的腳色，又為了因應高速資料傳輸量的需求，使得本地振盪源需要操作在較高頻率，如何產生一個低功耗、低相位雜訊且低抖動量的本地振盪源，在現代通訊系統中是值得研究的。而四相位本地振盪源可以應用於抑制鏡像訊號，以及通訊系統的調變、解調變。本論文主要針對K頻段的四相位本地振盪源，以達到低功耗、低相位雜訊及低抖動量之研究。第二章闡述一個K頻段自我注入耦合四相位壓控振盪器之電路分析、設計及量測結果。第三章闡述一個K頻段變壓器耦合式次諧波注入鎖定四相位壓控振盪器之電路分析、設計以及量測結果。第四章則為不同模態的訊號源分析比較及具鎖頻迴路自對準之次諧波注入鎖定四相位壓控振盪器之電路設計與量測結果。本論文的設計均採用台積電提供的90奈米互補式金氧半場效電晶體製程(TSMC 90 nm GUTM CMOS)。
第二章介紹數種四相位振盪器的耦合架構及設計原理，並且提出自我注入耦合的方法，並使用電流再利用及變壓器回授的方法降低相位雜訊，且使用位元控制器來增加振盪器的可調頻寬，同時實現一個K頻段自我注入耦合四相位壓控振盪器，量測頻率為18.1到21.4 GHz，可調頻寬為3.3 GHz相當於16.7%比例頻寬，距載波偏移1 MHz的相位雜訊為-109 dBc/Hz，相位誤差及振幅誤差分別為0.28°及0.13dB，電路直流總功耗為8.4 mW。
第三章介紹注入鎖定及倍頻器的架構及設計原理，並且提出變壓器耦合式的注入鎖定的方法，並使用電流再利用的方法降低直流功耗，且使用自我注入耦合的方式產生四相位訊號，同時實現一個K頻段變壓器耦合式次諧波注入鎖定四相位壓控振盪器，輸出頻率從22.9到25 GHz，可調範圍大約為2.1 GHz，以十六分之一訊號注入後，鎖定頻寬約為200MHz，在距載波偏移1 MHz的相位雜訊為-120.7 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz為37.1 fs。最小四相位誤差及振幅誤差分別為0.02°及0.35 dB，電路直流總功耗為7.2 mW。
第四章為具鎖頻迴路自對準之次諧波注入鎖定四相位振盪器。首先介紹理論模型及轉移函數，接著利用ADS(advance design system)軟體進行模擬分析鎖頻迴路以及各種不同的頻率合成器架構的相位雜訊及抖動量，量測的鎖頻範圍為22.9到25GHz，各個控制電壓的鎖定範圍約為200 MHz，輸出功率大於-10 dBm。距載波偏移1 MHz的相位雜訊為-119.4 dBc/Hz，抖動量積分範圍由1 kHz到40 MHz為36.7 fs，最小四相位誤差及振幅誤差分別為0.44°及0.1 dB電路直流總功耗為40 mW，和過去文獻比較擁有最佳的優化指數(FOM)。

摘要(英)

In radio frequency (RF) transceiver circuit, local oscillator (LO) is an indispensable building block, since the demand for high data transmission rate is increasing, Design a high-frequency, low power, low phase noise and low jitters LO is an important issue.LO with quadrature outputs in RF transceiver is for the applications of image rejection and modulation/demodulation. This thesis focuses on K-band LO with quadrature outputs to achieve low power consumption, low phase noise and low jitters. Analysis, design and measured results for K-band quadrature voltage-controlled oscillator (QVCO) using self-injection coupled (SIC) topology are proposed in Chapter 2. Analysis and design of the K-band sub-harmonic injection-locked QVCO (SILQVCO) using transformer coupled (TC) topology are proposed in Chapter 3. Analysis, design and measured results for a K-band TC-SILQVCO with frequency-locked loop (FLL) self-alignment are proposed in Chapter 5. All of the designs in this thesis are fabricated using TSMC 90 nm GUTM CMOS process.
Several topologies of QVCO are introduced in Chapter 2. The SIC-coupled, current reused and transformer feedback are investigated to obtain the design methodology. Also, the bit-controller is used to increase tunning range. The proposed K-band SIC-QVCO features a tunning range of 3.3 GHz and a 16.7% fractional bandwidth, the measured phase noise at 1 MHz offset is -109 dBc/Hz. The minimum quadrature phase and amplitude error are 0.28° and 0.13 dB respectively, and the DC power consumption is 8.4 mW.
Several frequency multiplier and the injection-locked theory are introduced in Chapter 3. The transformer coupled approach is adopted in VCO design, and the proposed VCO using self-injection coupled technique can generate quadrature signal. TC-SILQVCO using current reused technique can be operated in lower DC power consumption. The measured locked range of the K-band TC-SILQVCO is from 22.9 to 25 GHz and locking range for each control voltage is about 200 MHz. The measured output power is higher than -10 dBm over the range. The measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -120.7 dBc/Hz and 37.1 fs, respectively. The minimum quadrature phase error and amplitude error are 0.02° and 0.35 dB, the total power consumption is 7.2 mW.
In Chapter 5, we proposed a K-band TC-SILQVCO with frequency-locked loop (FLL) self-alignment. First, analysis of the FLL, including the theoretical models, transfer functions and models using ADS (advance design system) software with system setup of each blocks in FLL. A theoretical model of the SILFLL is proposed, and the calculated phase noise and jitter are presented for the comparison of various topologies frequency synthesizer. The measured locked range of the SILFLL is from 22.9 to 25 GHz, and the locking range for each control voltages is about 200 MHz. The measured output power is higher than -10 dBm over the range. The measured phase noise (1 MHz offset) and RMS jitter (integrated from 1 kHz to 40 MHz) are -119.4 dBc/Hz and 36.7 fs, respectively. The total DC power consumption is about 40 mW, and this work has the best FOM as compared with literatures.

關鍵字(中)

★ K頻段
★ 注入鎖定
★ 壓控振盪器
★ 四相位
★ 互補式金氧半場效電晶體
★ 鎖頻迴路
★ 低相位雜訊

關鍵字(英)

★ K-band
★ Injection locking
★ Voltage-Control-Oscillator
★ Quadrature
★ CMOS
★ Frequency-Locked-Loop
★ Low phase Noise

論文目次

摘要 I
Abstract III
目錄 V
圖目錄 VIII
表目錄 XVI
第1章緒論 1
1.1 研究動機及背景 1
1.2 相關研究及發展現況 1
1.3 貢獻 3
1.4 論文架構 3
第2章 K頻段自我注入四相位壓控振盪器 5
2.1 簡介 5
2.2 四相位振盪器架構概述[103] 7
2.2.1 Coupled LC tank四相位振盪器耦合方式 9
2.2.2 自我注入耦合[77] 11
2.3 電路設計及分析 12
2.3.1 製程介紹 12
2.3.2 電流再利用及變壓器回授分析[79] 13
2.3.3 線性振盪條件分析[61] 24
2.3.4 四相位訊號耦合電路分析 25
2.3.5 耦合電晶體設計 30
2.3.6 位元控制設計 32
2.3.7 電路模擬結果 34
2.3.8 相位雜訊貢獻模擬結果 38
2.4 電路實現及實驗結果與討論 40
2.4.1 SIC-QVCO量測 41
2.4.2 SIC-QVCO量測除錯 48
2.5 總結 50
第3章 K頻段變壓器耦合式次諧波注入鎖定四相位壓控振盪器 52
3.1 簡介 52
3.2 注入鎖定原理與頻率倍頻器介紹 54
3.2.1 注入鎖定原理概述[65] 54
3.2.2 倍頻器介紹 57
3.3 電路設計及分析 61
3.3.1 線性振盪條件分析[61] 63
3.3.2 LC共振腔的相位偏移量及鎖定範圍分析[108] 63
3.3.3 透過變壓器注入分析[108] 67
3.3.4 注入電晶體偏壓條件 70
3.3.5 四相位耦合訊號分析 73
3.3.6 脈衝產生器 74
3.4 電路實現及實驗結果與討論 77
3.4.1 次諧波注入鎖定四相位振盪器及鎖定範圍量測 79
3.4.2 次諧波注入鎖定四相位振盪器及鎖定範圍量測 87
3.5 總結 91
第4章具鎖頻迴路自對準之K頻段次諧波注入鎖定四相位壓控振盪器 93
4.1 簡介 93
4.2 具鎖頻迴路自對準之次諧波注入鎖定壓控振盪器[59] 96
4.2.1 SILFLL系統模擬[147] 97
4.2.1.1 波德圖穩定度分析 98
4.2.1.2 閉迴路暫態分析 101
4.2.2 SILFLL相位雜訊分析 102
4.3 電路實現 108
4.3.1 電流模式邏輯(CML)除頻器 109
4.3.2 相位偵測器及頻率偵測器[141] 111
4.4 電路實現及實驗結果與討論 115
4.4.1 鎖相迴路量測 118
4.4.2 次諧波注入鎖相迴路量測 123
4.4.3 SILFLL量測 128
4.4.4 SILFLL相位雜訊除錯 133
4.4.5 SILFLL相位誤差量測 136
4.4.6 溫度變異量測 142
4.5 總結 144
第5章結論 146
附錄:四相位振盪器之相位誤差及振幅誤差量測 147
參考文獻 153

參考文獻

[1] T. Musch, “A high precision 24-GHz FMCW radar based on a fractional-N ramp-PLL, ” in IEEE Transactions on Instrumentation and Measurement, vol. 52, no. 2, pp. 324-327, April 2003.
[2] M. Klotz and H. Rohling, “24 GHz radar sensors for automotive applications, ” 13th International Conference on Microwaves, Radar and Wireless Communications. MIKON - 2000. Conference Proceedings (IEEE Cat. No.00EX428), Wroclaw, 2000, pp. 359-362 vol.1.
[3] B. Afshar and A. M. Niknejad, “A robust 24 mW 60 GHz receiver in 90 nm standard CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 182–183.
[4] K. Kang, F. Lin, D.-D. Pham, J. Brinkhoff, C.-H. Heng, Y. X. Guo, and X. Yuan, “A 60-GHz OOK receiver with an on-chip antenna in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1720–1731, Sep. 2010.
[5] A. Arbabian, S. Callender, S. Kang, B. Afshar, J.-C. Chien, and A.Niknejad, “A 90 GHz hybrid switching pulsed-transmitter for medicalimaging,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2667–2681,Dec. 2010.2113, Aug. 2010.
[6] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp.1606-1617, Jul. 2011.
[7] A. Arbabian, S. Kang, S. Callender, J.-C. Chien, B. Afshar, and A.Niknejad, “A 94 GHz mm-wave to baseband pulsed-radar for imagingand gesture recognition,” IEEEInt. Symp. on VLSI Design, Automation and Test,Jun. 2012, pp. 56-57.
[8] A. Arbabian, S. Callender, S. Kang, M. Rangwala, and A. Niknejad, “A 94 GHz mm-wave-to-baseband pulsed-radar transceiver with applications in imaging and gesture recognition,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 1055–1071, Apr. 2013. M.-W. Li, P.-C. Wang, T.-H. Huang, and H.-R. Chuang, “Low-voltage, wide-locking-range, millimeter-wave divide-by-5 injection-locked frequency divider,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 679-685, Mar. 2012.
[9] J. Lee, M. Liu, and H. Wang, “A 75-GHz phase-locked loop in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008.
[10] K.-H. Tsai and S.-I. Liu, “A 43.7mW 96GHz PLL in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 276-277, Feb. 2009.
[11] C. Lee and S.-I. Liu, “A 58-to-60.4GHz frequency synthesizer in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers, pp. 196-596, Feb. 2007.
[12] H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, and R. Fujimoto, “A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS,” Proc. Eur. Solid State Circuits Conf., pp. 472-475, Sept. 2007.
[13] K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, “A 57-to-66GHz quadrature PLL in 45nm digital CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 494-495, Feb. 2009.
[14] C. Lee, L.-C. Cho, J.-H. Wu, and S.-I. Liu, “A 50.8-53GHz clock generator using a harmonic-locked PD in 0.13-μm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 5, pp. 404-408, May 2008.
[15] K.-H. Tsai and S.-I. Liu, “A 62–66.1GHz phase-locked loop in 0.13um CMOS technology,” in IEEE Int. VLSI Design, Automation and Test, pp.113-116, Apr. 2008.
[16] H.-K. Chen, T. Wang, and S.-S. Lu, “A millimeter-wave CMOS triple-band phase-locked loop With A Multimode LC-Based ILFD,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1327-1338, May 2011.
[17] S. Kang, J.-C. Chien, and A. M. Niknejad, “A 100GHz phase-locked loop in 0.13μm SiGe BiCMOS process,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., pp.1-4, Jun. 2011.
[18] S. Shahramian, A. Hart, A. Tomkins, A. C. Carusone, P. Garcia, P. Chevalier, and S. P. Voinigescu, “Design of a dual W- and D-band PLL,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1011-1022, May 2011.
[19] K.-H. Tsai and S.-I. Liu, “A 104-GHz phase-locked loop using a VCO at second pole frequency,” IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 1, pp. 80-88, Jan. 2012.
[20] B.-Y. Lin and S.-I. Liu, “A 132.6-GHz phase-locked loop in 65 nm digital CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 58, no. 10, pp. 617-621, Oct. 2011.
[21] T.-Y. Chang, C.-S. Wang, and C.-K. Wang, “A low power W-band PLL with 17-mW in 65-nm CMOS technology,” in Proc. IEEE Asian Solid-State Circuits Conf., pp. 81-84, Nov. 2011.
[22] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004.
[23] G. Reddy Gangasani, P. Kinget, “Injection-lock dynamics in non-harmonic oscillators,” Circuits and Systems 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp. 4 pp.-1678, 2006.
[24] A. Mirzaei and H. Darabi, “Mutual pulling between two oscillators,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 360–372, Feb. 2014.
[25] H. Jia, L. Kuang, Z. Wang, and B. Chi, “A W-band injection-locked frequency doubler based on top-injected coupled resonator,” IEEE Trans. Microw. Theory Techn., vol. 64, no. 1, pp. 210–218, Jan. 2016.
[26] E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, “Injection-locked CMOS frequency doublers for μ-Wave and mm-Wave applications,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1565–1574, Aug. 2010.
[27] E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, “A 6 mW, 115 GHz CMOS injection-locked frequency doubler with differential output,” in Proc. Int. Conf. IC Design and Technology (ICICDT), Jun. 2010, pp. 236–239.
[28] A. Mazzanti, E. Monaco, M. Pozzoni ,F. Svelto “A 13.1% Tuning Range 115GHz Frequency Generator Based on Injection-Locked Frequency Doubler in 65nm CMOS”, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 2010.
[29] C. Leifso and J. Nisbet, “A monolithic 6 GHz quadrature frequency doubler with adjustable phase offset,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 405–412, Feb. 2006.
[30] Z. Chen and P. Heydari, “An 85–95.2 GHz transformer-based injection-locked frequency tripler in 65-nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2010, pp. 776–779.
[31] Y. Yeh and H. Chang, “A W-band wide locking range and low dc power injection-locked frequency tripler using transformer coupled technique,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 2, pp. 860–870, Feb. 2013.
[32] W. K. Chan and J. R. Long, “A 56–65 GHz injection-locked frequency tripler with quadrature outputs in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739–2746, Dec. 2008.
[33] S.-W. Tam, E. Socher, A. Wong, Y. Wang, L. D. Vu, and M.-C. F. Chang, “Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communications in CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2008, pp. 131–134.
[34] C.-N. Kuo and T.-C. Yan, “A 60 GHz injection-locked frequency tripler with spur suppression,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 10, pp. 560–562, Oct. 2010.
[35] M.-C. Chen and C.-Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1869–1878, Aug. 2008.
[36] Y.-L. Yeh, C.-S. Huang, and H.-Y. Chang, “A 20.7% locking range W-band fully integrated injection-locked oscillator using 90 nm CMOS technology,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012.
[37] N. M. and E. S., “Analysis and Design of an X-Band-to-W-Band CMOS Active Multiplier with Improved Harmonic Rejection,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 5, pp. 1924–1933, Feb. 2013.
[38] C.-C. Wang, Z. Chen, and P. Heydari, “W-band silicon-based frequency synthesizers using injection-locked and harmonic triplers,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1307–1320, May 2012.
[39] F.-H. Huang and Y.-M. Hsin, “A V-band frequency tripler with output power enhancement in 90 nm CMOS,” in Proc. 4th Int. HSIC, May 2012, pp. 1–4.
[40] N. Mazor, O. Katz, B. Sheinman, R. Carmon, R. Ben-Yishay, R. Levinger, A. Bruetbart, and D. Elad, “A high suppression frequency tripler for 60-GHz transceivers,” in Proc. IEEE MTT-S Int. Dig., May 2015, pp. 1–4.
[41] Y.-A. Lin, T.-H. Lin, and H.-Y. Chang, “A 42–71 GHz 90 nm CMOS injection-locked voltage-controlled oscillator using bulk injection technique,” in Proc. Eur. Microw. Integr. Circuits Conf., Sep. 2015, pp. 108–111.
[42] K. Kamogawa, T. Tokumitsu, and I. Toyoda, “A 20-GHz-band subharmonically injection-locked oscillator MMIC with wide locking range,” IEEE Microw. Guided Wave Lett., vol. 7, no. 8, pp. 233–235, Aug. 1997.
[43] F.-H. Huang, C.-K. Lin, and Y.-J. Chan, “V-band GaAs pHEMT cross-coupled sub-harmonic oscillator,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 8, pp. 473–475, Aug. 2006.
[44] L. Ye, H. Liao, and R. Huang, “A CMOS W-band ×4 frequency multiplier with cascading push-pull frequency doublers,” in Proc. Asia–Pacific Microw. Conf., 2012, pp. 166–168.
[45] Yu-Sheng Lin, Cheng-Han Wu, Chun-Chi Su, Yeong-Her Wang, “A Low-Power K-Band Frequency Quintupler with Current-Reused and Harmonic-Enhanced Technique”, IEEE Microw. Wireless Compon. Lett., vol. 24, pp. 701-703, 2014, ISSN 1531-1309.
[46] I. Kallfass, H. Massler, A. Tessmann, A. Leuther, M. Schlechtweg, and G. Weimann, “A broadband frequency sixtupler MIMIC for the W-band with > 7 dBm output power and > 6 dB conversion gain,” in IEEE Int. MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 2169–2172.
[47] U. J. Lewark, A. Tessmann, H. Massler, A. Leuther, and I. Kallfass, “Active single ended frequency multiplier-by-nine MMIC for millimeter-wave imaging applications,” in Proc. Wkshp. Integr. Nonlinear Microw. Millimetre-Wave Circuits, 2011, pp. 1–4.。
[48] N. Mazor and E. Socher, “X-band to W-band frequency multiplier in 65 nm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 8, pp. 424–426, Aug. 2012.
[49] C.-C. Wang, Z. Chen, and P. Heydari, “W-Band silicon-based frequency synthesizers using injection-locked and harmonic triplers,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1307-1320, May 2012.
[50] L. Ye, Y. Wang, C. Shi, H. Liao, and R. Huang, “A W-band divider-less cascading frequency synthesizer with push-push ×4 frequency multiplier and sampling PLL in 65nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., pp.1-3, Jun. 2012.
[51] A. Tang, D. Murphy, G. Virbila, F. Hsiao, S.-W. Tam, H.-T. Yu, H.-H. Hsieh, C.-P. Jou, Y. Kim, A. Wong, A. Wong, Y.-C. Wu, and M.-C. F. Chang, “D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology,” in IEEE MTT-S Int. Microw. Symp. Dig., pp.1-3, Jun. 2012.
[52] G. Liu, A. Trasser, and H. Schumacher, “A 64–84-GHz PLL with low phase noise in an 80-GHz SiGe HBT technology,” IEEE Trans Microw. Theory Tech., vol. 60, no. 12, pp. 3739-3748, Dec. 2012.
[53] A. Musa, R. Murakami, T. Sato, W. Chaivipas, K. Okada, and A. Matsuzawa, “A low phase noise quadrature injection locked frequency synthesizer for mm-wave applications,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp.2635-2649, Nov. 2011.
[54] C.-Y. Wu, M.-C. Chen, and Yi-Kai Lo, “A phase-locked loop with injection-locked frequency multiplier in 0.18-μm CMOS for V-Band applications,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1629-1636, Jul. 2009.
[55] C.-L. Wei, T.-K. Kuan, and S.-I. Liu, “A Subharmonically InjectionLocked PLL With Calibrated Injection Pulsewidth,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 62, no. 6, pp. 548-552, Jun. 2015.
[56] Y. C. Huang and S. I. Liu, “A 2.4 GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 417–428, Feb. 2013.
[57] F. Liang and K. J. Hsiao, “An injection-locked ring PLL with self-aligned injection window,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011, pp. 90–92.
[58] P.-H. Feng, and S.-H. Liu, “A Current-reused injection-locked frequency multiplication/division circuit in 40-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1523-1532, Apr. 2013.
[59] Y.-L. Yeh, S.-Y. Huang, Y.-E. Shen, and H.-Y. Chang, “A 90 nm CMOS low phase noise sub-harmonically injection-locked voltage-controlled oscillator with FLL self-alignment technique,” in IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, CA, USA, May 2016, pp. 1–4.
[60] Hong-Yeh Chang, Chun-Ching Chan, Ian Yi-En Shen, Yen-Liang Yeh, Shu-Yan Huang, ”Design and Analysis of CMOS Low-Phase-Noise Low-Jitter Subharmonically Injection-Locked VCO With FLL Self-Alignment Technique”, IEEE Trans. Microw. Theory Tech., vol. 64, pp. 4632-4645, 2016.
[61] B. Razavi, RF Microelectronics, Prentice-Hall, 1998.
[62] 高曜煌，射頻鎖相迴路IC設計，第二章，滄海書局，民國94年。
[63] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed MilimeterWave Wireless Systems,” IEEE ICCSC 2008, pp. 812-815.
[64] F. Maloberti and M. Signorelli, “Quadrature Waveform Generator with Enhanced Performances,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 222-226, 1998.
[65] 劉深淵、楊清淵，鎖相迴路，滄海書局，民國100年。
[66] H.-Y. Chang, Y.-H. Cho, M.-F. Lei, C.-S. Lin, T.-W. Huang, and H. Wang, “A 45-GHz quadrature voltage controlled oscillator with a reflection-type IQ modulator in 0.13-m CMOS technology,” in IEEE MTT-S Int. Microwave Symp. Dig., June 2006, pp. 739-742.
[67] S. Ko, J.-G. Kim, T. Song, E. Yoon, and S. Hong, “20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers,” in IEEE RFIC Symp. Dig., Jun 2004, pp. 269–272.
[68] M. Hossain and A. Chan Carusone, “20 GHz low power QVCO and de-skew techniques in 0.13-m digital CMOS,” in IEEE Custom Integrated Circuits Conf. pp. 447-450, 2008.
[69] S. Hackl, J. Bock, G. Ritzberger, M. Wurzer, and A. L. Scholtz “A 28-GHz monolithic integrated quadrature oscillator in SiGe Bipolar Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135-137, January 2003.
[70] W. L. Chan, H. Veenstra, and J. R. Long, “A 32GHz quadrature LC-VCO in 0.25μm SiGe BiCMOS technology,” in 2005 Int. Solid-State Circuit Conf. Dig., San Francisco, USA, pp. 538-539.
[71] C.-H. Lin and H.-Y. Chang, “A low phase noise low DC power quadrature voltage-controlled oscillator using a 0.18-m CMOS process,” in Proc. EuMIC, pp. 28-29, Sept. 2009.
[72] C.-L. Yang and Y.-C. Chiang, “Low phase-noise low-power CMOS VCO constructed in current-reused configuration,” IEEE Microw. and Wireless Compon. Lett., vol. 18, no. 2, pp. 136-138, Feb. 2008.
[73] H.-Y. Chang, and Y.-T. Chiu, “K-band CMOS differential and quadrature voltage-controlled oscillators for low phase-noise and low-power applications,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 46–59, Jan. 2012.
[74] S.-Y. Lee and C.-Y. Chen, “Analysis and digital of a wide-tuning-range VCO with quadrature outputs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 12, pp. 1209-1213, Dec. 2008.
[75] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 873-887, Jun. 2001.
[76] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737-1747, Dec. 2002.
[77] C.-H. Lin, and H.-Y. Chang, “A low-phase-noise CMOS quadrature voltage-controlled oscillator with self-injeciton-coupled technique,” IEEE Transactions on Circuit and System II, Exp. Briefs. vol. 59, no. 10, pp. 623-627, Oct. 2012.
[78] 林紀賢，注入鎖定非線性單晶微波積體電路之研究，國立中央大學電機工程研究所博士論文，民國101年。
[79] 邱垣達，低功耗低相位雜訊差動及四相位單晶片微波積體電路壓控振盪器之研究，國立中央大學電機工程研究所碩士論文，民國100年。
[80] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. of Solid-State Circuits, vol. 40, no. 3, pp. 652–660, Mar. 2005.
[81] S. Yun, S. Shin, H. Choi, and S. Lee, “A 1 mW current-reuse CMOS differential LC-VCO with low phase noise,” in Proc. IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 540–541.
[82] H. H. Hsieh and L. H. Lu, “A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations,” in IEEE MTT-S Int. Microwave Symp. Digest, vol. 55, pp. 467-473, March 2007.
[83] H. S. Choi, Q. D. Bui, and C.-S. Park, “A Low-Power CMOS VCO for 2.4GHz WLAN,” in Compound Semiconductor Integrated Circuit Symposium, 2007. CSIC 2007. IEEE, pp. 1–4, Oct 2007.
[84] J. Yang, C. Kim, D. Kim, and S. Hong, “Design of a 24 GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 3, pp. 173–177, Mar. 2010.
[85] Sonnet Software Inc., Sonnet User’s Manual, Release 13, North Syracuse, NY, Jun. 2011.
[86] Majid Jalalifar, Gyung-Su Byun, “A Current-Reused Back-Gate Coupling QVCO Using Transformer Feedback Structure,” IEEE Microw. and Wireless Compon. Lett., vol. 26, pp. 534-536, 2016.
[87] T. D. Loveless, S. Jagannathan, E. X. Zhang, D. M. Fleetwood, J. S. Kauppila, T. D. Haeffner, L. W. Massengill, “Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology,” IEEE Transactions on Nuclear Science, vol. 64, pp. 204-211, 2017.
[88] S. Saberi and J. Paramesh, “A 11.5–22 GHz dual-resonance transformer-coupled quadrature VCO,” in Proc. IEEE RFIC, 2011, pp. 1–4.
[89] M.-H. Li, Y.-H. Liao, and H.-Y. Chang, “A K-band low power high accuracy quadrature VCO using gate-modulated coupling and transformer feedback technique,” in Proc. Asia Pacific Microw. Conf., pp. 895–897, 2014.
[90] H.-Y. Chang and Y.-T. Chiu, “K-band CMOS differential and quadrature voltage-controlled oscillators for low phase-noise and low-power applications,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 1, pp. 46–59, Jan. 2012.
[91] Chi-Hsien Lin, Yu-Cheng Liu, Yen-Liang Yeh, Han-Chi Chiu, and Hong-Yeh Chang, “A 60-GHz low dc power self-injection coupling CMOS quadrature voltage-controlled oscillator with high quadrature accuracy,” IEEE International Microwave Symposium 2013.
[92] N.-C. Kuo, J.-C. Chien, and A. Niknejad, “Design and analysis on bidirectionally and passively coupled QVCO with nonlinear coupler,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 4, pp. 1130–1141, Apr. 2015.
[93] P.-Y. Wang, Y.-C. Chang, K.-H. Chuang, D.-C. Chang, and S. S. H. Hsu, “A low phase-noise 24 GHz CMOS quadrature-VCO using PMOS source-follower coupling technique,” in Proc. Euro. Microw. Conf., pp. 572–575, 2014.
[94] W. L. Chan, J. R. Long, “A 56-to-65 GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90-nm CMOS”, IEEE J. of Solid-State Circuits, Vol. 43, no. 12, pp. 2739-2746, December 2008.
[95] A. Musa et al., “A 58-63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS,” A-SSCC Dig. Tech. Papers, pp.189-192, November 2010.
[96] G. Mangraviti, “A 52-66GHz Subharmonically Injection-Locked Quadrature Oscillator with 10 GHz Locking Range in 40nm LP CMOS,” RFIC Symposium, pp. 309–312, June 2012
[97] A. E. Sieman, Lasers, CA: University Science Books, 1986.
[98] R. R. Ward, The living Clocks, New York: Alfred Knopf, 1971.
[99] C. Mao, C. S. Nallani, S. Sankaran, E. Seok, and K. K. O, “125-GHz diode frequency doubler in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1531-1538, May 2009.
[100] Y. Lee, J. R. East, and L. P. B. Katehi, “High efficiency W-band GaAs monolithic frequency multipliers,” IEEE Trans. Microw. Theory Tech., vol. 52, pp. 529-535, Feb. 2004.
[101] Y. Lee, J. R. East, and L. P. B. Katehi, “High efficiency W-band GaAs monolithic frequency multipliers,” IEEE Trans. Microw. Theory Tech., vol. 52, pp. 529-535, Feb. 2004.
[102] U. R. Pferiffer, C.Mishra, R. M. Rassel, S. Pinkett, and S. K. Reynolds, “Schottky barrier diode circuits in silicon for future millimeter-wave and Terahertz applications,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 2, pp. 364-371, Feb. 2008.
[103] 廖彥涵，微波毫米波寬頻振盪器與鎖相迴路之研製，國立中央大學電機工程研究所碩士論文，民國102年。
[104] “Optimization of quadrature modulator performance,” Technical Notes and Articles, RF Micro Devices Inc
[105] R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5–10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862–1872, Nov. 2004.
[106] L.-C. Cho, C. Lee, and S.-I. Liu, “A 1.2-V 37-38-GHz eight-phase clock generator in 0.13-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 42, pp. 1261-1270, Jun. 2007.
[107] S. Kang et al., “A W-band low-noise PLL with a fundamental VCO in SiGe for millimeter-wave applications,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 10, pp. 2390–2404, Oct. 2014.
[108] 葉彥良，應用於微波及毫米波鎖相迴路之金氧半場效電晶體注入鎖定振盪器研究，國立中央大學電機工程研究所博士論文，民國102年。
[109] C.-S. Lin, P.-S. Wu, M.-C. Yeh, J.-S. Fu, H.-Y. Chang, K.-Y. Lin, and H. Wang, “Analysis of multiconductor coupled-line Marchand baluns for miniature MMIC design,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 6, pp. 1190-1199, June 2007.
[110] Y.-G. Kim, K. W. Kim, and Y.-K. Cho, “A planar ultra-wideband balanced doubler,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 1243-1246.
[111] R. Bitzer, “Planar broadband MIC balanced frequency doublers,” in IEEE MTT-S Int. Microw. Symp. Dig., July 1991, vol. 1, pp. 273-276.
[112] S. A. Maas and Y. Ryu, “A broadband, planar, monolithic resistive frequency doubler,” in IEEE MTT-S Int. Microw. Symp. Dig., May 1994, vol. 1, pp. 443-446.
[113] Bryllert, A. Malko, J. Vukusic, and J. Stake, “A 25-75 GHz miniature double balanced frequency doubler in 0.18-μm CMOS Technology,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 4, pp. 275-277, Apr. 2008.
[114] D. Shim, C. Mao, S. Sankaran, and K. K. O, “150 GHz complementary anti-parallel diode frequency tripler in 130 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 1, pp. 43-45, Jan. 2011.
[115] T. Kiuru, J. Mallat, A. V. Raisanen, and T. Narhi, “Compact broadband MMIC Schottky frequency tripler for 75–140 GHz”, in Proc. Eur. Micro. Integr. Circuits Conf., Oct. 2011, pp. 108-111
[116] Y. Wang, W. L. Goh, Y.-Z. Xiong, “A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS,” in IEEE Int. Solid-State Circuits Conf., Tech. Dig., Feb. 2012, pp. 262-264.
[117] Y. Campos-Roca, C. Schworer, A. Leuther, and M. Seelmann-Eggebert “G-band metamorphic HEMT-based frequency multiplier,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 7, pp. 2893–2992, Jul. 2006
[118] A. Boudiaf, D. Bachelet, and C. Rumelhard, “A high-efficiency and low-phase-noise 38 GHz pHEMT MMIC tripler,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp. 2546–2553, Dec. 2000.
[119] J. C. Chiu, C. P. Chang, M. P. Houng, and Y. H.Wang, “A 12–36 GHz PHEMT MMIC balanced frequency tripler,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 1, pp. 19–21, Jan. 2006.
[120] Y. Campos-Roca, L. Verweyen, M. Fernandez-Barciela, E. Sanchez, M. C. Curras-Francos, W. Bronner, A. Hulsmann, and M. Schlechtweg, “An optimized 25.5–76.5 GHz PHEMT-based coplanar frequency tripler,” IEEE Microw. Guided Wave Lett., vol. 10, no. 6, pp. 242–244, Jun. 2000.
[121] N.-C. Kuo, Z.-M. Tsai, K. Schmalz, J. C. Scheytt, and H. Wang, “A 52-75 GHz frequency quadrupler in 0.25-μm SiGe BiCMOS process”, in Proc. Eur. Micro. Integr. Circuits Conf., Sept. 2010, pp. 365-368.
[122] E. Ojefors, B. Heinemann and U. R. Pfeiffer, “A 325 GHz Frequency Multiplier Chain in a SiGe HBT Technology,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig. May 2010, pp. 91-94.
[123] E. Ojefors, B. Heinemann, and U. R. Pfeiffer, “Active 220- and 325-GHz frequency multiplier chains in an SiGe HBT technology,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1311-1318, May 2011.
[124] J.-H. Chen, and H. Wang, “A high gain, high power K-band frequency doubler in 0.18 μm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 9, pp. 522-524, Sept. 2010.
[125] K. Y. Lin, J. Y. Huang, and S. C. Shin, “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Mircow. Wireless Compon. Lett., vol. 19, no. 5, pp. 308-310, May 2009.
[126] K. Yamamoto, “A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique,” IEEE J. Solid State Circuits, vol. 40, no. 6, pp. 1288-1295, Jun. 2005.
[127] N.-C. Kuo, J.-C. Kao, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 60-GHz frequency tripler with gain and dynamic-range enhancement,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 3, pp. 660-671, Mar. 2011.
[128] U. J. Lewark, A. Tessmann, H. Massler, S. Wagner, A. Leuther, and I. Kallfass, “300 GHz active frequency-tripler MMICs,” in Proc. Eur. Micro. Integr. Circuits Conf., Sept. 2011, pp. 236-339.
[129] F. Giannini and G. Leuzzi, Nonlinear Microwave Circuit Design, John Wiley & Sons, Ltd, England, 2004.
[130] S. Kishimoto, K. Maruhashi, M. Ito, T. Morimoto, Y. Hamada, and K. Ohata, “A 60-GHz-band subharmonically injection locked VCO MMIC operating over wide temperature range,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2005, pp. 1689–1692.
[131] K. Kamogawa, T. Tokumitsu, and M. Aikawa, “Injection-locked oscillator chain: A possible solution to millimeter-wave MMIC synthesizers,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 9, pp. 1578–1584, Sept. 1997.
[132] C.-Y. Wu and C.-Y. Yu, “Design and analysis of a millimeter-wave direct injection-locked frequency divider with large frequency locking range,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 8, pp. 1649–1658, Aug. 2007.
[133] C.-K. Hsieh, K.-Y. Kao, J. R. Tseng, and K.-Y. Lin, “A K-band CMOS low power modified Colpitts VCO using transformer feedback,” in IEEE MTT-S Int Microw. Symp. Dig., June 2009, pp. 1293–1296.
[134] Steve C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd edition.
[135] J. Lee, and H. Wang, ”Study of subharmonically injection-locked PLLs,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009.
[136] S. Hackl, J. Bock, G. Ritzberger, M. Wurzer, and A. L. Scholtz “A 28-GHz monolithic integrated quadrature oscillator in SiGe Bipolar Technology,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135-137, January 2003.
[137] Fredrik Tillman, Niklas Troedsson and Henrik Sjoland, “A 1.2 volt 1.8GHz CMOS quadrature front-end,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 362–365, Jun. 2004.
[138] A. Rofougaran, J. Rael, M. Rofougaran, A. Abidi, “A 900 MHz LC-oscillator with quadrature outputs,” in 1996 Int. Solid-State Circuit Conf. Dig., San Francisco, USA, pp. 392-393.
[139] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1737-1747, Dec. 2002.
[140] Y. C. Chang, Y. C. Hsu, S. G. Lin, Y. Z. Juang, and H. K. Chiou, “On-wafer single contact quadrature accuracy measurement using receiver mode in four-port vector network analyzer,” IEEE MTT-S Int. Microwave Symp. Dig., pp. 371–374, 2008.
[141] R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-m CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, Nov. 2004.
[142] B. M. Helal, C.-M. Hsu, K. Johnson, and M. H. Perrott, “A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning Loop,” IEEE J. Solid-State Circuits, vol. 44, pp. 1391-1400, May 2009.
[143] I-T. Lee, Y.-J. Chen, S.-I. Liu, C.-P. Jou, F.-L. Hsueh, and H.-H. Hsieh, “A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing ” IEEE Int. Solid-State Circuits Conf., Tech. Dig., pp. 414-415, Feb. 2013.
[144] Y.-C. Huang and S.-I. Liu, “A 2.4 GHz sub-harmonically injection-locked PLL with self-calibrated injection timing” IEEE Int. Solid-State Circuits Conf., Tech. Dig., pp. 338-341, Feb. 2012.
[145] B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, “A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,” IEEE J. Solid-State Circuits, vol. 43, pp. 855-863, Apr. 2008.
[146] F.-R. Liao and S.-S. Lu, ”A programmable edge-combining DLL with a current-splitting charge pump for spur suppression,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, pp. 946-950, Dec. 2010.
[147] 詹駿清，毫米波注入鎖定振盪器及鎖頻迴路之研究，國立中央大學電機工程研究所碩士論文，民國104年。
[148] 黃書彥，鎖頻迴路及追蹤與保持放大器之研製，國立中央大學電機工程研究所碩士論文，民國104年。
[149] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “A 40 GHz Power Efficient Static CML Frequency Divider in 0.13-μm CMOS Technology for High Speed MilimeterWave Wireless Systems,” IEEE ICCSC 2008, pp. 812-815.
[150] A. Pottbacker, U. Langmann, and H.-U. Schreiber “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992.
[151] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 117-121, Feb. 2009.
[152] D. B. Lesson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE., vol. 54, pp. 329-330, Feb. 1966.
[153] H.-Y. Chang, Y.-L. Yeh, Y.-C. Liu, M.-H. Li, and K. Chen, “A low jitter low phase noise 10-GHz sub-harmonically injectionlocked PLL with self-aligned DLL in 65 nm CMOS technology,” IEEE Trans. Microw. Theory & Techn., vol. 62, no. 03, pp. 543-555, Mar. 2014.
[154] 李昇洺，V及D頻段高除頻數注入鎖定除頻器與四相位鎖頻迴路之研製，國立中央大學電機工程研究所碩士論文，民國106年。
[155] D. Shin, S. Park, S. Raman and K. J. Koh, “A subharmonically injection-locked PLL with 130 fs RMS jitter at 24 GHz using synchronous reference pulse injection from nonlinear VCO envelope feedback, ” 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, 2017, pp. 100-103.
[156] D. Shin, S. Raman and K. J. Koh, “2.8 A mixed-mode injection frequency-locked loop for self-calibration of injection locking range and phase noise in 0.13μm CMOS, ” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 50-51.
[157] S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “19.2 A PVT-robust ?39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600μW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers, ” 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 324-325.
[158] K. Okada et al., “A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c, ” in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2988-3004, Dec. 2011.
[159] T. Siriburanon et al., “A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad, ” in IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1246-1260, May 2016.

指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2017-9-29

推文