一個可重組二值影像處理器及其開發平台設計

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姓名

張瑞慶(Jui-Ching Chang) 查詢紙本館藏

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資訊工程學系

論文名稱

一個可重組二值影像處理器及其開發平台設計
(Design of A Reconfigurable Binary Image Processor and Its Development Platform)

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摘要(中)

二值影像處理被運用在多種靜態及串流影像當中，如物件辨識、追蹤、除雜訊，為了適應各種領域不同應用，以及即時影像處理的需求，本研究提出一可重組二值影像處理器以及開發平台，具有高度靈活性與即時影像處理之優點，能夠透過程式控制改變影像處理流程，處理器使用pipeline架構設計，提供形態學與邏輯運算元以及連通元件標記演算法，可重組的特點包含影像大小、二值化門檻值、結構元素及二值影像處理流程。本研究透過合成於Stratix V FPGA平台來驗證硬體效能，其中有16顆運算核心，處理器頻率可達379.94MHz，一秒鐘能夠處理362張大小為"1024×1024" 的影像，並整合基因演算法及簡易開發平台，讓應用系統可以快速的開發，實驗結果證明本系統達到即時二值影像處理，能因應未來各領域之需求。

摘要(英)

Binary image processing has considerable applications in image and video processing such as object recognition, tracking, and denoising. To enable real-time image processing for various applications, we propose a reconfigurable binary image processor with a flexible development platform and real-time processing capabilities. The developed processor enables the modification of image processing procedures by reprogramming the employed hardware registers. The processor involves a pipeline architecture design which can perform morphological and binary operations and connected-component labeling. The reconfigurable features of the processor include the image size, image thresholding, structure element, and binary image processing procedure. For performance validation, the processor was implemented on a Stratix V field-programmable gate array, which can process approximately 362 frames per second and can conduct 16 operations with a 1024 × 1024 image at 379.94 MHz. Moreover, proposed platform with a genetic algorithm can be utilized for rapidly and conveniently developing the application system. The experimental results demonstrated that the processor is suitable for use in real-time applications of binary image processing.

關鍵字(中)

★ 可重組
★ 二值影像處理器
★ 數學形態學
★ 基因演算法
★ Real time

關鍵字(英)

★ Reconfigurable
★ Binary image processor
★ Mathematical morphology
★ Genetic algorithm
★ Real time

論文目次

摘　要 I
Abstract II
謝誌 III
目錄 V
圖目錄 VIII
表目錄 XIII
第一章、緒論 1
1.1 研究背景 1
1.2 研究目的 3
1.3 論文架構 4
第二章、文獻回顧 5
2.1 數學形態學與二值邏輯運算元 5
2.1.1 侵蝕 8
2.1.2 膨脹 9
2.1.3 Hit and miss transform 11
2.1.4 二值邏輯運算元 13
2.2 連通元件標記 16
2.3 結構元素分解 23
2.4 可重組二值影像處理器 25
第三章、可重組二值影像處理器架構 27
3.1 可重組二值影像處理器架構 27
3.2 指令輸入控制器 28
3.3 影像前處理模組 29
3.4 形態學與邏輯運算控制器 30
3.5 可重組形態學及二值影像處理核心 31
3.6 可重組二值影像開發控制器 36
3.7 軟硬體整合介面 36
第四章、系統實作 38
4.1 MIAT系統設計方法論 38
4.1.1 IDEF0 40
4.1.2 GRAFCET 42
4.2 系統架構IDEF0 45
4.2.1 應用控制器 46
4.2.2 二值影像控制器 47
4.2.3 資料介面 48
4.2.4 影像傳輸模組 49
4.2.5 影像前處理器 50
4.2.6 SPI接收控制器 51
4.2.7 SPI傳輸控制器 51
4.2.8 形態學核心 52
4.2.9 連通元件標記模組 53
4.3 GRAFCET離散事件建模 54
4.3.1 應用控制器 55
4.3.2 二值影像處理器 57
4.3.3 介面模組 58
4.3.4 影像傳輸模組 59
4.3.5 SPI接收控制器與傳輸控制器 61
4.3.6 影像前處理器 63
4.3.7 連通元件標記模組 64
4.3.8 形態學核心 66
4.4 系統合成 69
4.4.1 軟體合成 69
4.4.2 硬體合成 69
第五章、軟硬體整合驗證 79
5.1 實驗平台 79
5.1.1 FPGA開發平台 79
5.1.2 MCU開發平台 80
5.1.3 影像感測器 80
5.2 音符辨識應用 82
5.3 二值影像處理器硬體驗證 85
5.4 應用開發軟體 90
5.5 相關研究比較 92
5.6 應用開發實驗 95
第六章、結論與未來展望 101
6.1 結論 101
6.2 未來展望 103
參考文獻 104
附錄 110

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指導教授

陳慶瀚(Ching-Han Chen)

審核日期

2018-3-5

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