自動辨識混合訊號電路中構成區塊及RLC元件之方法

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姓名

王俊(Chun Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

自動辨識混合訊號電路中構成區塊及RLC元件之方法
(Automatic Recognition of Building Blocks and RLC Components in Mixed-Signal Circuits)

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摘要(中)

隨著電路製程的演進，混合訊號系統的積體電路設計變得越來越複雜，加速類比與數位混合訊號模擬的時間，是現在驗證單晶片系統設計中很重要的一環，以硬體描述語言建立類比電路的行為模型，是一種有效率的混合訊號系統驗證方式，為了將設計者的電路自動轉換成行為模型，在本論文中提出一套有效率的電路架構分析流程，可以自動從電路規格或連線關係萃取出混合訊號設計中的構成區塊，被動RLC元件將辨識獨立出來，有利于電晶體的辨識與轉換，且建構出一個架構分析平台，將Netlist檔案自動轉換成Verilog檔案，將設計的層級從電晶體層級拉到行為階層，達到加速混合訊號系統電路模擬的效果且有效地協助設計者減少額外工作時間，由幾個電路上的實驗結果來看，我們所提出的自動辨識平台確實能夠正確辨識出對應的電路，並維持模擬結果的準確度。

摘要(英)

The design and development of analog/mixed-signal (AMS) integrated circuits is becoming increasingly complex as technologies advances. Speeding up analog and mixed signal simulation is becoming more important in SoC design verification. Modeling analog circuit blocks by hardware description language and building their behavioral models is an efficient approach for verifying AMS systems. To transform any designer circuits into their respective behavioral models automatically, in this thesis, we proposed an efficient structure analysis flow that can extract building blocks in mixed-signal design automatically based on given circuit specifications and netlist. Moreover, passive RLC components within the circuits are analyzed independently and then removed from the circuits before the transistor structure analysis and transforming processes. This is accomplished by a structure analysis platform for transforming Spice Netlist files into Verilog automatically, and transforming transistor-level design into behavior-level design. Achieves the purpose of speeding up AMS system simulation and reduces verification time and complexity for designers. As shown in the experimental results on several circuits, the proposed approach is able to achieve correct recognition of the respective given circuits instantaneously.

關鍵字(中)

★ 辨識
★ 混合訊號

關鍵字(英)

★ recognition
★ mixed-signal

論文目次

摘要 v
Abstract vi
致謝 vii
Contents viii
List of Figures x
List of Tables i
Chapter One: Introduction 1
1- 1 Motivation 1
1- 2 Problem Formation 7
1- 3 Outline 8
Chapter Two: Background Information 9
2- 1 Spice Netlist Format 10
2- 2 Graph Representation 12
2- 3 Related Works 14
2-3-1 SubGemini 14
2-3-2 Resource Management 16
2-3-3 DC Connect Component Partition Method 18
Chapter Three: Structure Analysis and Verilog File Generation Platform 20
3- 1 Structure Analysis and Verilog File Generation Platform Flow 20
3- 2 Pre-processing Work 22
3-2-1 Uniform device name 23
3-2-2 Encode 25
3- 3 Top-Down Screen Analysis 28
3-3-1 Sub-circuit Structure Analysis 30
3-3-2 DC Connect Analysis 33
3-3-3 Vertical Grouping for Analog Structure Analysis (VGFA) 37
3-3-4 Horizontal Grouping for Analog Structure Analysis (HGFA) 40
3- 4 Output Verilog File 42
Chapter Four: RLCD Components 44
4- 1 RLCD Components Analysis 44
4- 2 RLCD Components Encoding Rules 46
4- 3 RLCD Components Removal 49
Chapter Five: Experimental Results 51
5- 1 Structure Analysis of a Two Stage OPA 51
5- 2 Structure Analysis of a Phase Lock Loop (PLL) 55
5- 3 Parallel-in/Serial-out System Simulation Results and Time Analysis 57
Chapter Six: Conclusion and Future Works 60
References 61

參考文獻

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指導教授

周景揚(Jing-Yang Jou)

審核日期

2018-1-29

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