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姓名	陳俊諺(Chun-Yen Chen)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	以逼零演算法實現無外部校正之單一自適應系統之5 Gbps全速率連續時間線性等化器與決策回授等化器 (A 5 Gbps Full-Rate CTLE and DFE Adopting the Single Adaptive System Using Zero-Forcing Algorithm without Off-Chip Calibration)
相關論文	★ 一種應用於觸控液晶顯示器的新型嵌入式開關 ★ 多重相位之延遲鎖定迴路倍頻器設計與分析 ★ 2.5Gbps串列收發器設計 ★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計 ★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路 ★ 全數位任意責任週期之同步映射延遲電路 ★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測 ★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統 ★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路 ★ 高解析度可變動責任週期之同步複製延遲電路 ★ 奈米CMOS晶片內序列傳輸之接收器 ★ 奈米CMOS晶片內序列傳輸之送器 ★ 基於鎖相迴路之多重相位脈波產生器 ★ 低能量時脈儲存元件之分析、設計與量測 ★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器 ★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計
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摘要(中)	隨著近年來製程發展以及晶片處理速度日益精進，資料傳遞頻寬皆日漸提升，傳統之並列傳輸方式已被串列傳輸所取代，例如電腦匯流排所使用之DisplayPort、PCI-Express、SATA、USB，或是光纖網路之SONET等規格都皆使用串列傳輸作為傳輸介面。資料通過傳輸通道會受到符碼間干擾的影響導致訊號完整度下降，因此等化器被廣泛應用於接收端以補償資料經過通道所導致的衰減。 本論文提出一個採用逼零演算法的自適應系統，可以分別調整連續時間線性等化器(Continuous time linear equalizer, CTLE)以及決策回授等化器(Decision feedback equalizer, DFE)在不同通道衰減下的補償量。傳統上要針對CTLE和DFE進行自適應演算，必須使用兩種不同的自適應回授路徑，因此本論文提出只用一種自適應回授路徑就可以調整這兩種等化器的補償大小，藉此達到降低硬體複雜度與減少整體功率消耗的效果，且由於此自適應系統可以分別對於CTLE以及DFE進行最佳化，所以可以針對更多不同大小的通道衰減進行補償。本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程實現，電路操作電壓為1 V，輸入資料速率為5 Gbps，輸入時脈頻率為5 GHz，通道衰減可用範圍為4 dB到27 dB，在通道衰減4 dB時，等化後資料的峰對峰值抖動量為30.22 ps，方均根抖動量為6.54 ps; 在通道衰減17 dB時，等化後資料的峰對峰值抖動量為42.67 ps，方均根抖動量為8.03 ps; 在通道衰減27 dB時，等化後資料的峰對峰值抖動量為56.44 ps，方均根抖動量為10.17 ps。在通道衰減27 dB時之整體功率消耗為12.5 mW，其中CTLE以及DFE之等化器功率消耗為5.5 mW，自適應機制電路之功率消耗為7 mW，晶片面積為1.46 mm2，其中核心電路面積為0.063 mm2。
摘要(英)	As the quantity demanded of consumer electronics is increasingly grossing, the communication system must be operated at the high speed. Therefore, the high-speed serial link has replaced parallel data buses as dominant input/output (I/O) devices for the data transmission today. However, when the data is transmitted at the high speed, there are heavily attenuated losses on the channel between transmitters (TXs) and receivers (RXs) since the bandwidth of channel is not enhanced. The large channel loss leads the transmitted bit to create the post-cursor in the long tail interfering in the next bit, and then the quality of data is attenuated and increases the bit error rate (BER). This phenomenon is called as the inter-symbol interference (ISI). Therefore, equalizers must be aopted to compensate for the channel loss. This thesis presents an adaptation system with the zero-forcing algorithm to adjust the continuous time linear equalizer (CTLE) and the one-tap decision feedback equalizer (DFE). Conventionally, there are two different adaptation systems to adjust the boost gain and the tap weighting of CTLE and DFE separately, which means that there are two different adaptation loops. Thus, the new adaptation loop which merged two loops of each equalizer types to a single adaptation loop. As a result, the complexity and power consumption of circuits are reduced. Because the flexibility of adaptive equalizers is improved, it can compensate channel losses from 4 dB to 27 dB and operate at the 5-Gbps data rate. The fabricated chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process. When the channel loss is 4 dB, the peak-to-peak jitter of equalized data is 30.22 ps and the root mean square (RMS) jitter is 6.54 ps. When channel loss is 17 dB, the peak-to-peak jitter of equalized data is 45.67 ps and the RMS jitter is 8.03 ps. When channel loss is 27 dB, the peak-to-peak jitter of equalized data is 56.44 ps and the RMS jitter is 10.17 ps. The power consumption is 12.5 mW at a supply voltage of 1 V and the channel loss of 27 dB. The entire equalizer and the overall adaptative system utilize 5.5 mW and 7 mW of power, respectively. The chip area is 1.46 mm2 and the core area is 0.063 mm2.
關鍵字(中)	★ 等化器 ★ 連續時間線性等化器 ★ 決策回授等化器 ★ 自適應系統 ★ 逼零演算法	關鍵字(英)	★ Equalizer ★ CTLE ★ DFE ★ Adaptive System ★ Zero-Forcing Algorithm ★ LMS Algorithm
論文目次	摘要i Abstractii 誌謝iii 目錄iv 圖目錄vii 表目錄xi 緒論1 研究動機1 論文架構4 高速串列傳輸之訊號完整性5 基本觀念5 隨機二位元資料特性5 資料編排形式6 傳輸線理論7 抖動分析11 隨機抖動(Random Jitter, RJ)12 定量性抖動(Deterministic Jitter, DJ)12 週期性抖動(Period Jitter, PJ)12 責任週期失真(Duty Cycle Distortion, DCD)13 資料相關抖動(Data Dependent Jitter, DDJ)14 單一位元脈衝響應與等化器之關係14 眼圖分析17 誤碼率18 等化器之背景簡介21 等化器電路的總類21 連續時間線性等化器(CTLE)22 決策回授等化器(DFE)23 前饋式回授等化器(FFE)24 自適應機制的種類25 頻譜平衡技術(Spectrum Balancing Technique)25 最小均方演算法(LMS)26 傳統自適應等化器電路28 傳統自適應線性等化器28 頻譜平衡技術之自適應線性等化器29 Sign-sign LMS技術之自適應決策回授等化器30 Sign-sign LMS之使用條件32 逼零演算法(Zero-forcing Algorithm)35 比較與討論36 具自適應之連續時間線性等化器與決策回授等化器設計與實現37 電路架構37 操作說明39 在具有ISI情況下之等化器補償情況39 行為模擬41 子電路介紹44 連續時間線性等化器(CTLE)44 一階決策回授等化器(1-Tap DFE)45 自適應逼零演算法(Adaptive Zero-forcing Algorithm)46 訊號序列偵測器(Data Pattern Detector)47 改良版LMS演算系統(Modified LMS Algorithm System)48 補償增益調整機制(Gain Adaptive System)49 自適應迴路切換機制(Adaptive Loop Switch)51 模擬結果53 通道模型53 具自適應之5 Gbps等化器模擬55 佈局前模擬55 短通道模擬(Channel Loss = 4 dB @ 2.5 GHz)55 長通道模擬(Channel Loss = 17 dB @ 2.5 GHz)57 佈局後模擬59 短通道模擬(Channel Loss = 4 dB @ 2.5 GHz)59 長通道模擬(Channel Loss = 17 dB @ 2.5 GHz)61 結果整理63 非理想通道佈局後模擬(Non-ideal Channel Loss = 17 dB @ 2.5 GHz)65 晶片佈局與量測67 電路佈局67 晶片封裝68 佈局規劃與電源規劃70 量測考量71 量測環境71 高頻輸出緩衝器72 高頻時脈輸入端73 M8048A ISI通道74 晶片與印刷電路板照相75 量測結果76 具自適應等化器量測76 不同訊號序列之補償結果81 量測與模擬結果之討論83 規格比較表86 結論87 結論87 未來研究方向88 參考文獻89
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指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2018-7-16
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