應用於深度神經網路系統內動態隨機存取記憶體之錯誤糾正碼式刷新功耗降低技術

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謝宗甫(Tsung-Fu Thsieh) 查詢紙本館藏

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論文名稱

應用於深度神經網路系統內動態隨機存取記憶體之錯誤糾正碼式刷新功耗降低技術
(ECC-Based Refresh Power Reduction Technique for DRAMs of Deep Neural Network Systems)

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摘要(中)

深度神經網路(DNN)被視為一個十分有應用價值的人工智慧技術。DNN系統通常需要以動態隨機記憶體(DRAM)來儲存數據。然而DRAM是一種十分耗電的元件，因此需要有針對DNN系統中用於降低DRAM功耗的技術。
本論文提出了一種混和投票機制與錯誤更正碼(Voting and error-correction code, VECC)的資料保護技術，通過延長DRAM的刷新週期來降低功耗。VECC以投票的方法保護在DNN中數值趨近於零的權重資料，並以錯誤糾正碼保護剩餘資料。以此種混合式的保護機制來糾正受到DRAM刷新周期延長而出現的資料失效(retention fault)。為了實現VECC的技術於DNN系統中，本論文提出了一個軟硬體結合的自我測試技術(Software-Hardware-Cooperated built-in self test, SHC-BIST)，用以蒐集在不同DRAM刷新周期下的資料錯誤資訊。此外也提出了相應的解碼以及重組硬體設計。
模擬結果顯示，在四個著名的DNN模組中，VECC可以節省至少93.7%的DRAM刷新功耗，且精準度損耗(accuracy loss)小於0.5%，而額外所需付出的錯誤檢驗碼位元數均小於原始資料的1%。

摘要(英)

Deep neural network (DNN) is considered as a practical and effective artificial intelligence technique.
A DNN system typically needs a dynamic random access memory (DRAM) for the storing
of data. However, DRAM is a power-hungry component. Effective techniques for reducing the
power consumption of the DRAM in a DNN system thus are needed.
In this thesis, a hybrid voting and error-correction code (VECC) technique is proposed to reduce
the refresh power of DRAMs in DNN systems by extending the DRAM refresh period. The
VECC technique takes advantage of the characteristics of wights of DNN model to reduce the cost
of check bits. Most of weights of a DNN model are close to zero. Therefore, the VECC technique
extends the refresh period of DRAMs by using the voting mechanism to protect weights being
close to zero from retention faults and using the error correction code (ECC) to protect weights
being not close to zero from retention faults. To realize the VECC technique, a software-hardwarecooperated
built-in self-test (SHC-BIST) scheme is proposed to test the cells with data retention
faults of the DRAM with respect to different refresh periods. Also, a decoding and remapping unit
is proposed to decode and remap the encoded weights.
Simulation results show that the proposed VECC technique can achieve up to 93.7% refresh
power saving for four typical DNN models with the adverse effect of inference accuracy loss less
than 0.5%, and the check bit overhead is less than 1%.
i

關鍵字(中)

★ 深度神經網路
★ 動態隨機記憶體
★ 刷新功耗
★ 資料壓縮
★ 自我測試

關鍵字(英)

★ Deep Neural Network
★ DRAM
★ redresh power
★ data compression
★ BIST

論文目次

1 Introduction 1
1.1 Deep Neural Network System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Deep Neural Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Neural Network Acceleration System . . . . . . . . . . . . . . . . . . . . 4
1.2 Dynamic Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 Organization of DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 DRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Block-Based Multiperiod Refresh Power Reduction . . . . . . . . . . . . . 8
1.3.2 ECC-Based Refresh Period Extending . . . . . . . . . . . . . . . . . . . . 11
1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Proposed VECC Technique for DRAM Refresh Period Extension 14
2.1 Characteristic of Weights in DNN Systems . . . . . . . . . . . . . . . . . . . . . . 14
2.2 VECC Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 En/Decoding & Refresh Period Extending Process . . . . . . . . . . . . . . . . . . 18
2.3.1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.2 Encoding Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 Decoding Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.4 Refresh Period Selection Flow . . . . . . . . . . . . . . . . . . . . . . . . 34
3 Hardware Design 42
3.1 VECC Decoder and Read Address Controller . . . . . . . . . . . . . . . . . . . . 42
3.2 Programmable BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Simulation Result 56
4.1 Accuracy Loss Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2 Power Saving Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3 Bits Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4 Read Latency Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5 Area Overhead Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5 Conclusion 68

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指導教授

李進福(Jin-Fu Li)

審核日期

2018-12-27

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