應用於衛星通訊之QFN封裝X-/Ku-Band 低雜訊放大器設計

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陳冠宇(Kuan-Yu Chen) 查詢紙本館藏

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電機工程學系

論文名稱

應用於衛星通訊之QFN封裝X-/Ku-Band 低雜訊放大器設計
(QFN-Packaged X-/Ku-Band LNA Design for Satellite Communication Applications)

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摘要(中)

本篇論文提出了三顆應用於衛星通訊之X-/Ku-Band低雜訊放大器電路設計，使用90-nm CMOS製程整合GIPD製程及0.15-μm GaAs pHEMT (P15)製程實現，擁有體積小、低雜訊與高增益等優點，並透過平面四邊無引腳(Quad Flat no-Lead,QFN)進行封裝，可以取代傳統LNB(Low Noise Block Downconverter)使用離散(Discrete)元件實現的放大器，達到縮小體積的目的。
第一個低雜訊放大器電路設計，我們利用90-nm CMOS製程整合GIPD製程實現。利用GIPD製程具有高阻值矽基板及低損耗的優勢來設計被動元件，以提升被動元件的Q值，並透過覆晶技術整合兩種製程，以達到低雜訊操作之目的。量測結果顯示此低雜訊放大器可於9.8 GHz提供18.8 dB增益，雜訊指數為3.5 dB，IIP3三階截斷點為-7 dBm。當操作電壓為1.2 V時，功耗為17.5 mW。
第二個低雜訊放大器電路設計，我們使用P15製程實現，並且使用QFN料件進行封裝，放大器擁有高增益、低雜訊指數、體積小等優點，且封裝後的晶片即可直接焊接於PCB(Print Circuit Board)與其他電路一起使用，非常具有實用性。為了確保封裝後的低雜訊放大器依然擁有良好的雜訊與功率匹配，我們使用3D電磁模擬軟體模擬QFN的寄生效應後，與LNA一同設計。量測結果顯示此低雜訊放大器擁有8.5 GHz-12.5 GHz的頻寬，可在9.7 GHz提供最高¬¬¬22.4 dB 之增益，在10.7 GHz雜訊指數僅有1.5 dB，IIP3 三階截斷點為¬¬¬¬-10 dBm，當操作電壓為1.1 V時，功耗¬為68.5 mW。
第三個低雜訊放大器電路設計使用P15製程實現，擁有能夠接收水平(Horizontally)極化以及垂直(Vertically)極化訊號的功能，並且使用QFN封裝雙極化低雜訊放大器，藉由控制第一級放大器的偏壓選擇不同埠的訊號，且擁有高增益、低雜訊指數、低功耗、體積小等優點，封裝後的晶片可直接焊接於PCB上與其他電路一起使用，非常具有實用性。量測結果顯示此低雜訊放大器水平埠與垂直埠均擁有10.7 GHz-13.2 GHz的頻寬，在12 GHz提供最高¬¬20.8 dB與21.5之增益，在頻帶中雜訊指數最低約為1.35 dB，IIP3三階截斷點分別為¬¬-11 dBm與-10 dBm，當操作電壓為1 V與0.8 V時，功耗為¬32.8 m W。

摘要(英)

In this thesis, three high-gain, low-noise, and compact X-/Ku-Band low-noise amplifiers (LNA) for the satellite communication application are proposed. These LNAs are realized in a 90-nm CMOS technology combined with GIPD process and 0.15-μm GaAs pHEMT technology with Quad Flat no-Leads (QFN) packaging. Replacing the discrete amplifiers in the Low Noise Block Downconverter (LNB) is to make the system more compact.
The first LNA design is realized in a 90-nm CMOS technology combined with GIPD process. Some of the passive components are designed on the GIPD process. Using the low metal loss substrate is to realize high quality factor of the passive components. Combining the 90-nm CMOS and GIPD process by using flip chip technique is to minimize the noise figure. The proposed LNA can provide power gain of 18.8 dB at 9.8 GHz and the minimum NF of 3.5 dB in the measurement. The IIP3 is -7 dBm. The power consumption is only 17.5 mW from a 1.2-V supply.
The second LNA design is realized in a 0.15-μm GaAs pHEMT technology with Quad Flat no-Leads (QFN) packaging. This is a low-noise, low-power consumption, high-gain, and compact LNA. This packaged LNA can be directly welded on the print circuit board (PCB) and be able to work with other circuits. The parasitic effect of the QFN packaging is completely characterized by using a 3D electromagnetic simulator and then is co-designed with the LNA to ensure simultaneous noise and impedance matching at the desired frequency band. The proposed packaged LNA exhibits measured power gain of 22.4 dB at 9.7 GHz while having 3-dB bandwidth from 8.5 to 12.5 GHz. The minimum NF is 1.5 dB at 10.7 GHz. The power consumption is only 68.5 mW from a 1.1-V supply.
The third LNA design is realized in a 0.15-μm GaAs pHEMT technology with Quad Flat no-Leads (QFN) packaging. The LNA is able to support the reception of dual horizontally (H) and vertically (V) polarized signals, increasing the channel capacity. This is a low-noise, low-power consumption, high-gain, and compact LNA. This packaged LNA can be directly welded on the print circuit board (PCB) and be able to work with other circuits. The proposed QFN-packaged LNA can provide power gain of 20.8 and 21.5 dB while having 3-dB bandwidth from 10.7 to 13.2 GHz and minimum NF of 1.35 dB for the H- and V-polarization channels respectively. The IIP3 is -11 dBm and -10 dBm for the H- and V-polarization channels respectively. The power consumption is only 32.8 mW from a 1-V and 0.8-V supply.

關鍵字(中)

★ 低雜訊放大器

關鍵字(英)

★ Low-Noise Amplifier

論文目次

摘要 I
Abstract II
誌謝 IV
目錄 V
圖目錄 VII
表目錄 XII
第一章緒論 1
1.1研究動機 1
1.2論文架構 6
第二章 90-nm CMOS整合GIPD之低雜訊放大器設計 7
2.1整合GIPD之90-nm CMOS低訊放大器簡介 7
2.2整合GIPD之90-nm CMOS低訊放大器設計 7
2.2.1 CMOS低訊放大器設計 7
2.2.2 GIPD 被動匹配電路設計 10
2.2.3覆晶連接結構簡介 12
2.2.4整合GIPD之90-nm CMOS低雜訊放大器設計流程 14
2.3整合GIPD之90-nm CMOS低雜訊放大器布局與量測考量 14
2.3.1 90-nm CMOS製程布局 14
2.3.2 GIPD製程布局 16
2.4整合GIPD之90-nm CMOS低雜訊放大器布局與量測結果 18
2.4.1整合GIPD之90-nm CMOS低雜訊放大器布局與量測考量與架設 18
2.4.2整合GIPD之90-nm CMOS低雜訊放大器模擬與量測結果 21
2.4.3.整合GIPD之90-nm CMOS低雜訊放大器量測結果討論 24

第三章使用QFN封裝之砷化鎵低雜訊放大器 26
3.1 使用QFN封裝之砷化鎵低雜訊放大器簡介 26
3.2 使用QFN封裝之砷化鎵低雜訊放大器設計 27
3.2.1 P15低雜訊放大器設計 27
3.2.2 QFN封裝架構設計 30
3.2.3使用QFN封裝之砷化鎵低雜訊放大器設計流程 32
3.2.4 使用QFN封裝之砷化鎵低雜訊放大器佈局 33
3.2.5 PCB 與L2L校正板的設計與佈局 33
3.2.6使用QFN封裝之砷化鎵低雜訊放大器量測架設與考量 35
3.2.7使用QFN封裝之砷化鎵低雜訊放大器模擬與量測比較 38
3.2.8使用QFN封裝之砷化鎵低雜訊放大器量測結果討論 41
3.3使用QFN封裝之砷化鎵低雜訊放大器第二版 43
3.3.1使用QFN封裝之砷化鎵低雜訊放大器第二版設計 43
3.3.2使用QFN封裝之砷化鎵低雜訊放大器第二版模擬與量測比較 46
3.3.3使用QFN封裝之砷化鎵低雜訊放大器第二版量測結果討論 49
第四章應用於衛星之X-/Ku-Band低雜訊放大器 52
4.1應用於衛星之X-/Ku-Band低雜訊放大器簡介 52
4.2應用於衛星之X-/Ku-Band低雜訊放大器設計 53
4.3 QFN封裝架構設計 57
4.4應用於衛星之X-/Ku-Band低雜訊放大器設計流程 60
4.5應用於衛星之X-/Ku-Band低雜訊放大器布局 61
4.6 PCB 與L2L校正板的設計與佈局 62
4.7應用於衛星之X-/Ku-Band低雜訊放大器量測架設與考量 63
4.8應用於衛星之X-/Ku-Band低雜訊放大器模擬與量測比較 64
4.9應用於衛星之X-/Ku-Band低雜訊放大器量測結果討論 69
第五章結論與未來展望 73
5.1總結............ 73
5.2未來發展 74
參考文獻 74

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指導教授

傅家相李俊興(Jia-Shiang Fu Chun-Hsing Li)

審核日期

2019-1-28

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