| 摘要(英) |
When a problem occurring on a wafer, it can be divided into two kinds of errors, random or systematic. In this study, we use previously proposed boomerang chart to classify the problem of real wafer (WM-811K).
However, with the advancement of technology, wafer size and quantity are also increasing. Therefore, our simulation must also re-create corresponding results in response to increasing size and quantity of wafer. This situation results in the need to simulate more kinds of random defects when constructing the boomerang chart. When the random defects and the size of the wafer increase at the same time, the simulation time of the previous algorithm will increase nonlinearly. In this study, we hope to use new algorithm to solve the previous problem.
This method not only speeds up the construction of the boomerang chart and the classification of the real wafer (WM-811K), making it possible to simulate bigger or larger numbers of wafers. The results can be obtained more quickly and will not be limited by the simulation environment. BA-19 can speed up 1423x on w48099，and it only cost 300 seconds to finish simulation. |
| 參考文獻 |
[1] J.E. Chen, M.J. Wang, Y.S. Chang, S.C. Shyu, and Y.Y. Chen, “Yield Improvement by Test Error Cancellation ”, Proceedings of the Fifth Asian Test Symposium (ATS’96), pp.258-262, Nov. 1996.
[2] C.K. Hsu, F. Lin, K.T. Cheng, W. Zhang, X. Li, J.M. Carulli, and K.M. Butler, “Test data analytics - Exploring spatial and test-item correlations in production test data”, in International Test Conference (ITC), pp.1-10, Sep. 2013.
[3] M.J. Wu, J.S.R. Jang, and J.L. Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-scale Datasets”, in IEEE Transactions on Semiconductor Manufacturing, vol.28, no.1, pp.1-12, Feb. 2015.
[4] F. Lin, C.K. Hsu, and K.T. Cheng, “Learning from Production Test Data: Correlation Exploration and Feature Engineering”, in Asian Test Symposium (ATS), pp.236-241, Nov. 2014.
[5] F. Lin, C.K. Hsu, and K.T. Cheng, “Feature engineering with canonical analysis for effective statistical tests screening test escapes”, in International Test Conference (ITC), pp.1-10, Oct. 2014.
[6] 林正田, “Wafer Map Analysis from a Random-Defect-Source Perspective” ，碩士論文，中央大學，2012.
[7] 曾國銓, “A Non-uniformly Distributed Defect Map Analysis by Quantification Model” ，碩士論文，中華大學，2013.
[8] 蕭寶威, “Wafer Map Analysis from Random Distributed Defects” ，碩士論文，中央大學，2016.
[9] 葉昱緯, “Application of Boomerang Chart to Real-World Mass Production Wafer Maps” ，碩士論文，中央大學，2016.
[10] 鄭育典, “An Accelerated C-Core for Calculating the Cluster Number in Wafer Map Analysis” ，碩士論文，中央大學，2018. |
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