快閃記憶體製程中蝕刻氮化矽產生之矽酸鹽在 二氧化矽表面的沉積:質傳限制

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姓名

鄧凱文(TENG KAI WEN) 查詢紙本館藏

畢業系所

化學工程與材料工程學系

論文名稱

快閃記憶體製程中蝕刻氮化矽產生之矽酸鹽在二氧化矽表面的沉積:質傳限制
(Deposition of silicate from Si3N4 etching onto SiO2 surfaces in flash memory manufacturing: mass transfer limitation)

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摘要(中)

在3D NAND 快閃記憶體晶片中的氮化矽層通常用熱磷酸來去除。然而，蝕刻氮化矽所產生的矽酸鹽產物所造成在二氧化矽層上異常的沉積行為將會對接下來的製程造成嚴重的影響。因此，我們製作了一個由兩個間隔80m的控片所形成的簡單系統來研究此沉積行為。為了瞭解此現象，不同因素的影響像是水含量(磷酸濃度)，以及攪拌程度的不同，將在此系統中被檢驗。我們發現，隨著水含量或者攪拌速率的增加，二氧化矽的沉積速率將隨之減少。實驗結果證實，在二氧化矽層的異常沉積現象是狹小空間中的化學沉積以及質傳兩個因素競爭所造成的結果。

摘要(英)

The Si3N4 layers in a 3D NAND flash patterned wafer are generally removed by hot phosphoric acid. However, the abnormal deposition of silicate which is the byproduct from Si3N4 etching onto the neighboring SiO2 layers will cause a serious problem in the following process. In this work, the abnormal deposition phenomenon was investigated by a simple system containing a narrow gap (~80 um) between two blanket wafers. To understand the mechanism, the influences of various factors on the chemical etching dynamics were examined, including the water content and the extent of mechanical agitation. It is found that the growth rate of SiO2 decreases as the water content or the extent of agitation is increased. Our experimental results reveal that the abnormal growth on SiO2 layers is a consequence of the competition between chemical deposition and mass transfer in a confined space (reaction-diffusion system).

關鍵字(中)

★ 蝕刻
★ 氮化矽
★ 磷酸
★ 半導體

關鍵字(英)

★ etch
★ silicon nitride
★ phosphoric acid
★ semi conductor

論文目次

摘要 i
ABSTRACT ii
誌謝 iii
LIST OF CONTENTS iv
LIST OF FIGURES v
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 EXPERIMENT 4
2-1 Materials 4
2-2 Apparatus 4
2-3 Fabrication of the Si3N4/SiO2 dual-wafer system 5
2-4 Experimental details 5
CHAPTER 3 RESULT AND DICUSSION 6
3-1 Effect of the water content on the etching rate 6
3-2 Deposition of silicate and abnormal growth 11
3-3 Agitation and mass transfer limitation of silicate 17
CHAPTER 4 CONCLUSION 21
CHAPTER 5 REFERENCE 23

參考文獻

[1] W.V. Gelder, V.E. Hauser, The etching of silicon nitride in phosphoric acid with silicon dioxide as a mask, J. Electrochem. Soc. 114.8 (1967) 869-872.
[2] Y.H. Chang, C.C. Hu, C.M. Yang, A design for selective wet etching of Si3N4/SiO2 in phosphoric acid using a single wafer processor, J. Electrochem. Soc. 165.4 (2018) H3187-H3191.
[3] Cho et al, Development of high selectivity phosphoric acid and its application to flash STI pattern, Electrochem. Soc. Trans. 45.6 (2012) 251-256.
[4] B. Derek, W. Printz, T. Furukawa, Etching of silicon nitride in 3D NAND structures, Electrochem. Soc. Trans. 69.8 (2015): 159-167.
[5] Hong et al, Compositions for etching and methods of forming a semiconductor device, United States patent. US 8,940,182 B2 (2015).
[6] Yu et al, Method and system for improving wet chemical bath process stability and productivity in semiconductor manufacturing, United States patent. US 2009/0087929 A1 (2009).
[7] H.S. Fogler, Elements of Chemical Reaction Engineering, third ed., Prentice Hall PTR, 2005.
[8] K.Morita, and K. Ohnaka, Novel selective etching method for silicon nitride films on silicon substrates by means of subcritical water, Industrial & engineering chemistry research. 39.12 (2000): 4684-4688.
[9] Buttet et al, Alternative to H3PO4 for Si3N4 removal by using chemical downstream etching, Electrochem. Soc. Trans. 64.39 (2015): 1-9.

指導教授

曹恆光(HENG KWONG TSAO)

審核日期

2019-6-27

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